ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C3 ESP32-C3 10 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) Copyright 2022 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. RV32IMC r0p0 little false false 4 false 32 32 0x00000000 0xFFFFFFFF AES AES (Advanced Encryption Standard) Accelerator AES 0x6003A000 0x0 0xBC registers AES 48 KEY_0 Key material key_0 configure register 0x0 0x20 KEY_0 This bits stores key_0 that is a part of key material. 0 32 read-write KEY_1 Key material key_1 configure register 0x4 0x20 KEY_1 This bits stores key_1 that is a part of key material. 0 32 read-write KEY_2 Key material key_2 configure register 0x8 0x20 KEY_2 This bits stores key_2 that is a part of key material. 0 32 read-write KEY_3 Key material key_3 configure register 0xC 0x20 KEY_3 This bits stores key_3 that is a part of key material. 0 32 read-write KEY_4 Key material key_4 configure register 0x10 0x20 KEY_4 This bits stores key_4 that is a part of key material. 0 32 read-write KEY_5 Key material key_5 configure register 0x14 0x20 KEY_5 This bits stores key_5 that is a part of key material. 0 32 read-write KEY_6 Key material key_6 configure register 0x18 0x20 KEY_6 This bits stores key_6 that is a part of key material. 0 32 read-write KEY_7 Key material key_7 configure register 0x1C 0x20 KEY_7 This bits stores key_7 that is a part of key material. 0 32 read-write TEXT_IN_0 source text material text_in_0 configure register 0x20 0x20 TEXT_IN_0 This bits stores text_in_0 that is a part of source text material. 0 32 read-write TEXT_IN_1 source text material text_in_1 configure register 0x24 0x20 TEXT_IN_1 This bits stores text_in_1 that is a part of source text material. 0 32 read-write TEXT_IN_2 source text material text_in_2 configure register 0x28 0x20 TEXT_IN_2 This bits stores text_in_2 that is a part of source text material. 0 32 read-write TEXT_IN_3 source text material text_in_3 configure register 0x2C 0x20 TEXT_IN_3 This bits stores text_in_3 that is a part of source text material. 0 32 read-write TEXT_OUT_0 result text material text_out_0 configure register 0x30 0x20 TEXT_OUT_0 This bits stores text_out_0 that is a part of result text material. 0 32 read-write TEXT_OUT_1 result text material text_out_1 configure register 0x34 0x20 TEXT_OUT_1 This bits stores text_out_1 that is a part of result text material. 0 32 read-write TEXT_OUT_2 result text material text_out_2 configure register 0x38 0x20 TEXT_OUT_2 This bits stores text_out_2 that is a part of result text material. 0 32 read-write TEXT_OUT_3 result text material text_out_3 configure register 0x3C 0x20 TEXT_OUT_3 This bits stores text_out_3 that is a part of result text material. 0 32 read-write MODE AES Mode register 0x40 0x20 MODE This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. 0 3 read-write ENDIAN AES Endian configure register 0x44 0x20 ENDIAN endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian 0 6 read-write TRIGGER AES trigger register 0x48 0x20 TRIGGER Set this bit to start AES calculation. 0 1 write-only STATE AES state register 0x4C 0x20 STATE Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. 0 2 read-only 16 0x1 IV_MEM[%s] The memory that stores initialization vector 0x50 0x8 16 0x1 H_MEM[%s] The memory that stores GCM hash subkey 0x60 0x8 16 0x1 J0_MEM[%s] The memory that stores J0 0x70 0x8 16 0x1 T0_MEM[%s] The memory that stores T0 0x80 0x8 DMA_ENABLE DMA-AES working mode register 0x90 0x20 DMA_ENABLE 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. 0 1 read-write BLOCK_MODE AES cipher block mode register 0x94 0x20 BLOCK_MODE Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. 0 3 read-write BLOCK_NUM AES block number register 0x98 0x20 BLOCK_NUM Those bits stores the number of Plaintext/ciphertext block. 0 32 read-write INC_SEL Standard incrementing function configure register 0x9C 0x20 INC_SEL This bit decides the standard incrementing function. 0: INC32. 1: INC128. 0 1 read-write AAD_BLOCK_NUM Additional Authential Data block number register 0xA0 0x20 AAD_BLOCK_NUM Those bits stores the number of AAD block. 0 32 read-write REMAINDER_BIT_NUM AES remainder bit number register 0xA4 0x20 REMAINDER_BIT_NUM Those bits stores the number of remainder bit. 0 7 read-write CONTINUE AES continue register 0xA8 0x20 CONTINUE Set this bit to continue GCM operation. 0 1 write-only INT_CLEAR AES Interrupt clear register 0xAC 0x20 INT_CLEAR Set this bit to clear the AES interrupt. 0 1 write-only INT_ENA AES Interrupt enable register 0xB0 0x20 INT_ENA Set this bit to enable interrupt that occurs when DMA-AES calculation is done. 0 1 read-write DATE AES version control register 0xB4 0x20 0x20191210 DATE This bits stores the version information of AES. 0 30 read-write DMA_EXIT AES-DMA exit config 0xB8 0x20 DMA_EXIT Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. 0 1 write-only APB_CTRL Advanced Peripheral Bus Controller APB_CTRL 0x60026000 0x0 0xA0 registers SYSCLK_CONF APB_CTRL_SYSCLK_CONF_REG 0x0 0x20 0x00000001 PRE_DIV_CNT reg_pre_div_cnt 0 10 read-write CLK_320M_EN reg_clk_320m_en 10 1 read-write CLK_EN reg_clk_en 11 1 read-write RST_TICK_CNT reg_rst_tick_cnt 12 1 read-write TICK_CONF APB_CTRL_TICK_CONF_REG 0x4 0x20 0x00010727 XTAL_TICK_NUM reg_xtal_tick_num 0 8 read-write CK8M_TICK_NUM reg_ck8m_tick_num 8 8 read-write TICK_ENABLE reg_tick_enable 16 1 read-write CLK_OUT_EN APB_CTRL_CLK_OUT_EN_REG 0x8 0x20 0x000007FF CLK20_OEN reg_clk20_oen 0 1 read-write CLK22_OEN reg_clk22_oen 1 1 read-write CLK44_OEN reg_clk44_oen 2 1 read-write CLK_BB_OEN reg_clk_bb_oen 3 1 read-write CLK80_OEN reg_clk80_oen 4 1 read-write CLK160_OEN reg_clk160_oen 5 1 read-write CLK_320M_OEN reg_clk_320m_oen 6 1 read-write CLK_ADC_INF_OEN reg_clk_adc_inf_oen 7 1 read-write CLK_DAC_CPU_OEN reg_clk_dac_cpu_oen 8 1 read-write CLK40X_BB_OEN reg_clk40x_bb_oen 9 1 read-write CLK_XTAL_OEN reg_clk_xtal_oen 10 1 read-write WIFI_BB_CFG APB_CTRL_WIFI_BB_CFG_REG 0xC 0x20 WIFI_BB_CFG reg_wifi_bb_cfg 0 32 read-write WIFI_BB_CFG_2 APB_CTRL_WIFI_BB_CFG_2_REG 0x10 0x20 WIFI_BB_CFG_2 reg_wifi_bb_cfg_2 0 32 read-write WIFI_CLK_EN APB_CTRL_WIFI_CLK_EN_REG 0x14 0x20 0xFFFCE030 WIFI_CLK_EN reg_wifi_clk_en 0 32 read-write WIFI_RST_EN APB_CTRL_WIFI_RST_EN_REG 0x18 0x20 WIFI_RST reg_wifi_rst 0 32 read-write HOST_INF_SEL APB_CTRL_HOST_INF_SEL_REG 0x1C 0x20 PERI_IO_SWAP reg_peri_io_swap 0 8 read-write EXT_MEM_PMS_LOCK APB_CTRL_EXT_MEM_PMS_LOCK_REG 0x20 0x20 EXT_MEM_PMS_LOCK reg_ext_mem_pms_lock 0 1 read-write FLASH_ACE0_ATTR APB_CTRL_FLASH_ACE0_ATTR_REG 0x28 0x20 0x00000003 FLASH_ACE0_ATTR reg_flash_ace0_attr 0 2 read-write FLASH_ACE1_ATTR APB_CTRL_FLASH_ACE1_ATTR_REG 0x2C 0x20 0x00000003 FLASH_ACE1_ATTR reg_flash_ace1_attr 0 2 read-write FLASH_ACE2_ATTR APB_CTRL_FLASH_ACE2_ATTR_REG 0x30 0x20 0x00000003 FLASH_ACE2_ATTR reg_flash_ace2_attr 0 2 read-write FLASH_ACE3_ATTR APB_CTRL_FLASH_ACE3_ATTR_REG 0x34 0x20 0x00000003 FLASH_ACE3_ATTR reg_flash_ace3_attr 0 2 read-write FLASH_ACE0_ADDR APB_CTRL_FLASH_ACE0_ADDR_REG 0x38 0x20 S reg_flash_ace0_addr_s 0 32 read-write FLASH_ACE1_ADDR APB_CTRL_FLASH_ACE1_ADDR_REG 0x3C 0x20 0x00400000 S reg_flash_ace1_addr_s 0 32 read-write FLASH_ACE2_ADDR APB_CTRL_FLASH_ACE2_ADDR_REG 0x40 0x20 0x00800000 S reg_flash_ace2_addr_s 0 32 read-write FLASH_ACE3_ADDR APB_CTRL_FLASH_ACE3_ADDR_REG 0x44 0x20 0x00C00000 S reg_flash_ace3_addr_s 0 32 read-write FLASH_ACE0_SIZE APB_CTRL_FLASH_ACE0_SIZE_REG 0x48 0x20 0x00000400 FLASH_ACE0_SIZE reg_flash_ace0_size 0 13 read-write FLASH_ACE1_SIZE APB_CTRL_FLASH_ACE1_SIZE_REG 0x4C 0x20 0x00000400 FLASH_ACE1_SIZE reg_flash_ace1_size 0 13 read-write FLASH_ACE2_SIZE APB_CTRL_FLASH_ACE2_SIZE_REG 0x50 0x20 0x00000400 FLASH_ACE2_SIZE reg_flash_ace2_size 0 13 read-write FLASH_ACE3_SIZE APB_CTRL_FLASH_ACE3_SIZE_REG 0x54 0x20 0x00000400 FLASH_ACE3_SIZE reg_flash_ace3_size 0 13 read-write SPI_MEM_PMS_CTRL APB_CTRL_SPI_MEM_PMS_CTRL_REG 0x88 0x20 SPI_MEM_REJECT_INT reg_spi_mem_reject_int 0 1 read-only SPI_MEM_REJECT_CLR reg_spi_mem_reject_clr 1 1 write-only SPI_MEM_REJECT_CDE reg_spi_mem_reject_cde 2 5 read-only SPI_MEM_REJECT_ADDR APB_CTRL_SPI_MEM_REJECT_ADDR_REG 0x8C 0x20 SPI_MEM_REJECT_ADDR reg_spi_mem_reject_addr 0 32 read-only SDIO_CTRL APB_CTRL_SDIO_CTRL_REG 0x90 0x20 SDIO_WIN_ACCESS_EN reg_sdio_win_access_en 0 1 read-write REDCY_SIG0 APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 REDCY_SIG0 reg_redcy_sig0 0 31 read-write REDCY_ANDOR reg_redcy_andor 31 1 read-only REDCY_SIG1 APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 REDCY_SIG1 reg_redcy_sig1 0 31 read-write REDCY_NANDOR reg_redcy_nandor 31 1 read-only FRONT_END_MEM_PD APB_CTRL_FRONT_END_MEM_PD_REG 0x9C 0x20 0x00000015 AGC_MEM_FORCE_PU reg_agc_mem_force_pu 0 1 read-write AGC_MEM_FORCE_PD reg_agc_mem_force_pd 1 1 read-write PBUS_MEM_FORCE_PU reg_pbus_mem_force_pu 2 1 read-write PBUS_MEM_FORCE_PD reg_pbus_mem_force_pd 3 1 read-write DC_MEM_FORCE_PU reg_dc_mem_force_pu 4 1 read-write DC_MEM_FORCE_PD reg_dc_mem_force_pd 5 1 read-write RETENTION_CTRL APB_CTRL_RETENTION_CTRL_REG 0xA0 0x20 RETENTION_LINK_ADDR reg_retention_link_addr 0 27 read-write NOBYPASS_CPU_ISO_RST reg_nobypass_cpu_iso_rst 27 1 read-write CLKGATE_FORCE_ON APB_CTRL_CLKGATE_FORCE_ON_REG 0xA4 0x20 0x0000003F ROM_CLKGATE_FORCE_ON reg_rom_clkgate_force_on 0 2 read-write SRAM_CLKGATE_FORCE_ON reg_sram_clkgate_force_on 2 4 read-write MEM_POWER_DOWN APB_CTRL_MEM_POWER_DOWN_REG 0xA8 0x20 ROM_POWER_DOWN reg_rom_power_down 0 2 read-write SRAM_POWER_DOWN reg_sram_power_down 2 4 read-write MEM_POWER_UP APB_CTRL_MEM_POWER_UP_REG 0xAC 0x20 0x0000003F ROM_POWER_UP reg_rom_power_up 0 2 read-write SRAM_POWER_UP reg_sram_power_up 2 4 read-write RND_DATA APB_CTRL_RND_DATA_REG 0xB0 0x20 RND_DATA reg_rnd_data 0 32 read-only PERI_BACKUP_CONFIG APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 0x00006480 PERI_BACKUP_FLOW_ERR reg_peri_backup_flow_err 1 2 read-only PERI_BACKUP_BURST_LIMIT reg_peri_backup_burst_limit 4 5 read-write PERI_BACKUP_TOUT_THRES reg_peri_backup_tout_thres 9 10 read-write PERI_BACKUP_SIZE reg_peri_backup_size 19 10 read-write PERI_BACKUP_START reg_peri_backup_start 29 1 write-only PERI_BACKUP_TO_MEM reg_peri_backup_to_mem 30 1 read-write PERI_BACKUP_ENA reg_peri_backup_ena 31 1 read-write PERI_BACKUP_APB_ADDR APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 BACKUP_APB_START_ADDR reg_backup_apb_start_addr 0 32 read-write PERI_BACKUP_MEM_ADDR APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 BACKUP_MEM_START_ADDR reg_backup_mem_start_addr 0 32 read-write PERI_BACKUP_INT_RAW APB_CTRL_PERI_BACKUP_INT_RAW_REG 0xC0 0x20 PERI_BACKUP_DONE_INT_RAW reg_peri_backup_done_int_raw 0 1 read-only PERI_BACKUP_ERR_INT_RAW reg_peri_backup_err_int_raw 1 1 read-only PERI_BACKUP_INT_ST APB_CTRL_PERI_BACKUP_INT_ST_REG 0xC4 0x20 PERI_BACKUP_DONE_INT_ST reg_peri_backup_done_int_st 0 1 read-only PERI_BACKUP_ERR_INT_ST reg_peri_backup_err_int_st 1 1 read-only PERI_BACKUP_INT_ENA APB_CTRL_PERI_BACKUP_INT_ENA_REG 0xC8 0x20 PERI_BACKUP_DONE_INT_ENA reg_peri_backup_done_int_ena 0 1 read-write PERI_BACKUP_ERR_INT_ENA reg_peri_backup_err_int_ena 1 1 read-write PERI_BACKUP_INT_CLR APB_CTRL_PERI_BACKUP_INT_CLR_REG 0xD0 0x20 PERI_BACKUP_DONE_INT_CLR reg_peri_backup_done_int_clr 0 1 write-only PERI_BACKUP_ERR_INT_CLR reg_peri_backup_err_int_clr 1 1 write-only DATE APB_CTRL_DATE_REG 0x3FC 0x20 0x02007210 DATE reg_dateVersion control 0 32 read-write APB_SARADC Successive Approximation Register Analog to Digital Converter APB_SARADC 0x60040000 0x0 0x68 registers APB_ADC 43 CTRL digital saradc configure register 0x0 0x20 0x40038240 SARADC_START_FORCE select software enable saradc sample 0 1 read-write SARADC_START software enable saradc sample 1 1 read-write SARADC_SAR_CLK_GATED SAR clock gated 6 1 read-write SARADC_SAR_CLK_DIV SAR clock divider 7 8 read-write SARADC_SAR_PATT_LEN 0 ~ 15 means length 1 ~ 16 15 3 read-write SARADC_SAR_PATT_P_CLEAR clear the pointer of pattern table for DIG ADC1 CTRL 23 1 read-write SARADC_XPD_SAR_FORCE force option to xpd sar blocks 27 2 read-write SARADC_WAIT_ARB_CYCLE wait arbit signal stable after sar_done 30 2 read-write CTRL2 digital saradc configure register 0x4 0x20 0x0000A1FE SARADC_MEAS_NUM_LIMIT enable max meas num 0 1 read-write SARADC_MAX_MEAS_NUM max conversion number 1 8 read-write SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, otherwise not 9 1 read-write SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, otherwise not 10 1 read-write SARADC_TIMER_TARGET to set saradc timer target 12 12 read-write SARADC_TIMER_EN to enable saradc timer trigger 24 1 read-write FILTER_CTRL1 digital saradc configure register 0x8 0x20 APB_SARADC_FILTER_FACTOR1 Factor of saradc filter1 26 3 read-write APB_SARADC_FILTER_FACTOR0 Factor of saradc filter0 29 3 read-write FSM_WAIT digital saradc configure register 0xC 0x20 0x00FF0808 SARADC_XPD_WAIT saradc_xpd_wait 0 8 read-write SARADC_RSTB_WAIT saradc_rstb_wait 8 8 read-write SARADC_STANDBY_WAIT saradc_standby_wait 16 8 read-write SAR1_STATUS digital saradc configure register 0x10 0x20 SARADC_SAR1_STATUS saradc1 status about data and channel 0 32 read-only SAR2_STATUS digital saradc configure register 0x14 0x20 SARADC_SAR2_STATUS saradc2 status about data and channel 0 32 read-only SAR_PATT_TAB1 digital saradc configure register 0x18 0x20 SARADC_SAR_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0 24 read-write SAR_PATT_TAB2 digital saradc configure register 0x1C 0x20 SARADC_SAR_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0 24 read-write ONETIME_SAMPLE digital saradc configure register 0x20 0x20 0x1A000000 SARADC_ONETIME_ATTEN configure onetime atten 23 2 read-write SARADC_ONETIME_CHANNEL configure onetime channel 25 4 read-write SARADC_ONETIME_START trigger adc onetime sample 29 1 read-write SARADC2_ONETIME_SAMPLE enable adc2 onetime sample 30 1 read-write SARADC1_ONETIME_SAMPLE enable adc1 onetime sample 31 1 read-write ARB_CTRL digital saradc configure register 0x24 0x20 0x00000900 ADC_ARB_APB_FORCE adc2 arbiter force to enableapb controller 2 1 read-write ADC_ARB_RTC_FORCE adc2 arbiter force to enable rtc controller 3 1 read-write ADC_ARB_WIFI_FORCE adc2 arbiter force to enable wifi controller 4 1 read-write ADC_ARB_GRANT_FORCE adc2 arbiter force grant 5 1 read-write ADC_ARB_APB_PRIORITY Set adc2 arbiterapb priority 6 2 read-write ADC_ARB_RTC_PRIORITY Set adc2 arbiter rtc priority 8 2 read-write ADC_ARB_WIFI_PRIORITY Set adc2 arbiter wifi priority 10 2 read-write ADC_ARB_FIX_PRIORITY adc2 arbiter uses fixed priority 12 1 read-write FILTER_CTRL0 digital saradc configure register 0x28 0x20 0x03740000 APB_SARADC_FILTER_CHANNEL1 configure filter1 to adc channel 18 4 read-write APB_SARADC_FILTER_CHANNEL0 configure filter0 to adc channel 22 4 read-write APB_SARADC_FILTER_RESET enable apb_adc1_filter 31 1 read-write SAR1DATA_STATUS digital saradc configure register 0x2C 0x20 APB_SARADC1_DATA saradc1 data 0 17 read-only SAR2DATA_STATUS digital saradc configure register 0x30 0x20 APB_SARADC2_DATA saradc2 data 0 17 read-only THRES0_CTRL digital saradc configure register 0x34 0x20 0x0003FFED APB_SARADC_THRES0_CHANNEL configure thres0 to adc channel 0 4 read-write APB_SARADC_THRES0_HIGH saradc thres0 monitor thres 5 13 read-write APB_SARADC_THRES0_LOW saradc thres0 monitor thres 18 13 read-write THRES1_CTRL digital saradc configure register 0x38 0x20 0x0003FFED APB_SARADC_THRES1_CHANNEL configure thres1 to adc channel 0 4 read-write APB_SARADC_THRES1_HIGH saradc thres1 monitor thres 5 13 read-write APB_SARADC_THRES1_LOW saradc thres1 monitor thres 18 13 read-write THRES_CTRL digital saradc configure register 0x3C 0x20 APB_SARADC_THRES_ALL_EN enable thres to all channel 27 1 read-write APB_SARADC_THRES1_EN enable thres1 30 1 read-write APB_SARADC_THRES0_EN enable thres0 31 1 read-write INT_ENA digital saradc int register 0x40 0x20 APB_SARADC_THRES1_LOW_INT_ENA saradc thres1 low interrupt enable 26 1 read-write APB_SARADC_THRES0_LOW_INT_ENA saradc thres0 low interrupt enable 27 1 read-write APB_SARADC_THRES1_HIGH_INT_ENA saradc thres1 high interrupt enable 28 1 read-write APB_SARADC_THRES0_HIGH_INT_ENA saradc thres0 high interrupt enable 29 1 read-write APB_SARADC2_DONE_INT_ENA saradc2 done interrupt enable 30 1 read-write APB_SARADC1_DONE_INT_ENA saradc1 done interrupt enable 31 1 read-write INT_RAW digital saradc int register 0x44 0x20 APB_SARADC_THRES1_LOW_INT_RAW saradc thres1 low interrupt raw 26 1 read-only APB_SARADC_THRES0_LOW_INT_RAW saradc thres0 low interrupt raw 27 1 read-only APB_SARADC_THRES1_HIGH_INT_RAW saradc thres1 high interrupt raw 28 1 read-only APB_SARADC_THRES0_HIGH_INT_RAW saradc thres0 high interrupt raw 29 1 read-only APB_SARADC2_DONE_INT_RAW saradc2 done interrupt raw 30 1 read-only APB_SARADC1_DONE_INT_RAW saradc1 done interrupt raw 31 1 read-only INT_ST digital saradc int register 0x48 0x20 APB_SARADC_THRES1_LOW_INT_ST saradc thres1 low interrupt state 26 1 read-only APB_SARADC_THRES0_LOW_INT_ST saradc thres0 low interrupt state 27 1 read-only APB_SARADC_THRES1_HIGH_INT_ST saradc thres1 high interrupt state 28 1 read-only APB_SARADC_THRES0_HIGH_INT_ST saradc thres0 high interrupt state 29 1 read-only APB_SARADC2_DONE_INT_ST saradc2 done interrupt state 30 1 read-only APB_SARADC1_DONE_INT_ST saradc1 done interrupt state 31 1 read-only INT_CLR digital saradc int register 0x4C 0x20 APB_SARADC_THRES1_LOW_INT_CLR saradc thres1 low interrupt clear 26 1 write-only APB_SARADC_THRES0_LOW_INT_CLR saradc thres0 low interrupt clear 27 1 write-only APB_SARADC_THRES1_HIGH_INT_CLR saradc thres1 high interrupt clear 28 1 write-only APB_SARADC_THRES0_HIGH_INT_CLR saradc thres0 high interrupt clear 29 1 write-only APB_SARADC2_DONE_INT_CLR saradc2 done interrupt clear 30 1 write-only APB_SARADC1_DONE_INT_CLR saradc1 done interrupt clear 31 1 write-only DMA_CONF digital saradc configure register 0x50 0x20 0x000000FF APB_ADC_EOF_NUM the dma_in_suc_eof gen when sample cnt = spi_eof_num 0 16 read-write APB_ADC_RESET_FSM reset_apb_adc_state 30 1 read-write APB_ADC_TRANS enable apb_adc use spi_dma 31 1 read-write CLKM_CONF digital saradc configure register 0x54 0x20 0x00000004 CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write CLKM_DIV_B Fractional clock divider numerator value 8 6 read-write CLKM_DIV_A Fractional clock divider denominator value 14 6 read-write CLK_EN reg clk en 20 1 read-write CLK_SEL Set this bit to enable clk_apll 21 2 read-write APB_TSENS_CTRL digital tsens configure register 0x58 0x20 0x00018000 TSENS_OUT temperature sensor data out 0 8 read-only TSENS_IN_INV invert temperature sensor data 13 1 read-write TSENS_CLK_DIV temperature sensor clock divider 14 8 read-write TSENS_PU temperature sensor power up 22 1 read-write TSENS_CTRL2 digital tsens configure register 0x5C 0x20 0x00004002 TSENS_XPD_WAIT the time that power up tsens need wait 0 12 read-write TSENS_XPD_FORCE force power up tsens 12 2 read-write TSENS_CLK_INV inv tsens clk 14 1 read-write TSENS_CLK_SEL tsens clk select 15 1 read-write CALI digital saradc configure register 0x60 0x20 0x00008000 APB_SARADC_CALI_CFG saradc cali factor 0 17 read-write CTRL_DATE version 0x3FC 0x20 0x02007171 DATE version 0 32 read-write ASSIST_DEBUG Debug Assist ASSIST_DEBUG 0x600CE000 0x0 0xA0 registers ASSIST_DEBUG 54 C0RE_0_MONTR_ENA ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG 0x0 0x20 CORE_0_AREA_DRAM0_0_RD_ENA reg_core_0_area_dram0_0_rd_ena 0 1 read-write CORE_0_AREA_DRAM0_0_WR_ENA reg_core_0_area_dram0_0_wr_ena 1 1 read-write CORE_0_AREA_DRAM0_1_RD_ENA reg_core_0_area_dram0_1_rd_ena 2 1 read-write CORE_0_AREA_DRAM0_1_WR_ENA reg_core_0_area_dram0_1_wr_ena 3 1 read-write CORE_0_AREA_PIF_0_RD_ENA reg_core_0_area_pif_0_rd_ena 4 1 read-write CORE_0_AREA_PIF_0_WR_ENA reg_core_0_area_pif_0_wr_ena 5 1 read-write CORE_0_AREA_PIF_1_RD_ENA reg_core_0_area_pif_1_rd_ena 6 1 read-write CORE_0_AREA_PIF_1_WR_ENA reg_core_0_area_pif_1_wr_ena 7 1 read-write CORE_0_SP_SPILL_MIN_ENA reg_core_0_sp_spill_min_ena 8 1 read-write CORE_0_SP_SPILL_MAX_ENA reg_core_0_sp_spill_max_ena 9 1 read-write CORE_0_IRAM0_EXCEPTION_MONITOR_ENA reg_core_0_iram0_exception_monitor_ena 10 1 read-write CORE_0_DRAM0_EXCEPTION_MONITOR_ENA reg_core_0_dram0_exception_monitor_ena 11 1 read-write CORE_0_INTR_RAW ASSIST_DEBUG_CORE_0_INTR_RAW_REG 0x4 0x20 CORE_0_AREA_DRAM0_0_RD_RAW reg_core_0_area_dram0_0_rd_raw 0 1 read-only CORE_0_AREA_DRAM0_0_WR_RAW reg_core_0_area_dram0_0_wr_raw 1 1 read-only CORE_0_AREA_DRAM0_1_RD_RAW reg_core_0_area_dram0_1_rd_raw 2 1 read-only CORE_0_AREA_DRAM0_1_WR_RAW reg_core_0_area_dram0_1_wr_raw 3 1 read-only CORE_0_AREA_PIF_0_RD_RAW reg_core_0_area_pif_0_rd_raw 4 1 read-only CORE_0_AREA_PIF_0_WR_RAW reg_core_0_area_pif_0_wr_raw 5 1 read-only CORE_0_AREA_PIF_1_RD_RAW reg_core_0_area_pif_1_rd_raw 6 1 read-only CORE_0_AREA_PIF_1_WR_RAW reg_core_0_area_pif_1_wr_raw 7 1 read-only CORE_0_SP_SPILL_MIN_RAW reg_core_0_sp_spill_min_raw 8 1 read-only CORE_0_SP_SPILL_MAX_RAW reg_core_0_sp_spill_max_raw 9 1 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_RAW reg_core_0_iram0_exception_monitor_raw 10 1 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_RAW reg_core_0_dram0_exception_monitor_raw 11 1 read-only CORE_0_INTR_ENA ASSIST_DEBUG_CORE_0_INTR_ENA_REG 0x8 0x20 CORE_0_AREA_DRAM0_0_RD_INTR_ENA reg_core_0_area_dram0_0_rd_intr_ena 0 1 read-write CORE_0_AREA_DRAM0_0_WR_INTR_ENA reg_core_0_area_dram0_0_wr_intr_ena 1 1 read-write CORE_0_AREA_DRAM0_1_RD_INTR_ENA reg_core_0_area_dram0_1_rd_intr_ena 2 1 read-write CORE_0_AREA_DRAM0_1_WR_INTR_ENA reg_core_0_area_dram0_1_wr_intr_ena 3 1 read-write CORE_0_AREA_PIF_0_RD_INTR_ENA reg_core_0_area_pif_0_rd_intr_ena 4 1 read-write CORE_0_AREA_PIF_0_WR_INTR_ENA reg_core_0_area_pif_0_wr_intr_ena 5 1 read-write CORE_0_AREA_PIF_1_RD_INTR_ENA reg_core_0_area_pif_1_rd_intr_ena 6 1 read-write CORE_0_AREA_PIF_1_WR_INTR_ENA reg_core_0_area_pif_1_wr_intr_ena 7 1 read-write CORE_0_SP_SPILL_MIN_INTR_ENA reg_core_0_sp_spill_min_intr_ena 8 1 read-write CORE_0_SP_SPILL_MAX_INTR_ENA reg_core_0_sp_spill_max_intr_ena 9 1 read-write CORE_0_IRAM0_EXCEPTION_MONITOR_RLS reg_core_0_iram0_exception_monitor_ena 10 1 read-write CORE_0_DRAM0_EXCEPTION_MONITOR_RLS reg_core_0_dram0_exception_monitor_ena 11 1 read-write CORE_0_INTR_CLR ASSIST_DEBUG_CORE_0_INTR_CLR_REG 0xC 0x20 CORE_0_AREA_DRAM0_0_RD_CLR reg_core_0_area_dram0_0_rd_clr 0 1 read-write CORE_0_AREA_DRAM0_0_WR_CLR reg_core_0_area_dram0_0_wr_clr 1 1 read-write CORE_0_AREA_DRAM0_1_RD_CLR reg_core_0_area_dram0_1_rd_clr 2 1 read-write CORE_0_AREA_DRAM0_1_WR_CLR reg_core_0_area_dram0_1_wr_clr 3 1 read-write CORE_0_AREA_PIF_0_RD_CLR reg_core_0_area_pif_0_rd_clr 4 1 read-write CORE_0_AREA_PIF_0_WR_CLR reg_core_0_area_pif_0_wr_clr 5 1 read-write CORE_0_AREA_PIF_1_RD_CLR reg_core_0_area_pif_1_rd_clr 6 1 read-write CORE_0_AREA_PIF_1_WR_CLR reg_core_0_area_pif_1_wr_clr 7 1 read-write CORE_0_SP_SPILL_MIN_CLR reg_core_0_sp_spill_min_clr 8 1 read-write CORE_0_SP_SPILL_MAX_CLR reg_core_0_sp_spill_max_clr 9 1 read-write CORE_0_IRAM0_EXCEPTION_MONITOR_CLR reg_core_0_iram0_exception_monitor_clr 10 1 read-write CORE_0_DRAM0_EXCEPTION_MONITOR_CLR reg_core_0_dram0_exception_monitor_clr 11 1 read-write CORE_0_AREA_DRAM0_0_MIN ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG 0x10 0x20 0xFFFFFFFF CORE_0_AREA_DRAM0_0_MIN reg_core_0_area_dram0_0_min 0 32 read-write CORE_0_AREA_DRAM0_0_MAX ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG 0x14 0x20 CORE_0_AREA_DRAM0_0_MAX reg_core_0_area_dram0_0_max 0 32 read-write CORE_0_AREA_DRAM0_1_MIN ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG 0x18 0x20 0xFFFFFFFF CORE_0_AREA_DRAM0_1_MIN reg_core_0_area_dram0_1_min 0 32 read-write CORE_0_AREA_DRAM0_1_MAX ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG 0x1C 0x20 CORE_0_AREA_DRAM0_1_MAX reg_core_0_area_dram0_1_max 0 32 read-write CORE_0_AREA_PIF_0_MIN ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG 0x20 0x20 0xFFFFFFFF CORE_0_AREA_PIF_0_MIN reg_core_0_area_pif_0_min 0 32 read-write CORE_0_AREA_PIF_0_MAX ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG 0x24 0x20 CORE_0_AREA_PIF_0_MAX reg_core_0_area_pif_0_max 0 32 read-write CORE_0_AREA_PIF_1_MIN ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG 0x28 0x20 0xFFFFFFFF CORE_0_AREA_PIF_1_MIN reg_core_0_area_pif_1_min 0 32 read-write CORE_0_AREA_PIF_1_MAX ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG 0x2C 0x20 CORE_0_AREA_PIF_1_MAX reg_core_0_area_pif_1_max 0 32 read-write CORE_0_AREA_PC ASSIST_DEBUG_CORE_0_AREA_PC_REG 0x30 0x20 CORE_0_AREA_PC reg_core_0_area_pc 0 32 read-only CORE_0_AREA_SP ASSIST_DEBUG_CORE_0_AREA_SP_REG 0x34 0x20 CORE_0_AREA_SP reg_core_0_area_sp 0 32 read-only CORE_0_SP_MIN ASSIST_DEBUG_CORE_0_SP_MIN_REG 0x38 0x20 CORE_0_SP_MIN reg_core_0_sp_min 0 32 read-write CORE_0_SP_MAX ASSIST_DEBUG_CORE_0_SP_MAX_REG 0x3C 0x20 0xFFFFFFFF CORE_0_SP_MAX reg_core_0_sp_max 0 32 read-write CORE_0_SP_PC ASSIST_DEBUG_CORE_0_SP_PC_REG 0x40 0x20 CORE_0_SP_PC reg_core_0_sp_pc 0 32 read-only CORE_0_RCD_EN ASSIST_DEBUG_CORE_0_RCD_EN_REG 0x44 0x20 CORE_0_RCD_RECORDEN reg_core_0_rcd_recorden 0 1 read-write CORE_0_RCD_PDEBUGEN reg_core_0_rcd_pdebugen 1 1 read-write CORE_0_RCD_PDEBUGPC ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG 0x48 0x20 CORE_0_RCD_PDEBUGPC reg_core_0_rcd_pdebugpc 0 32 read-only CORE_0_RCD_PDEBUGSP ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG 0x4C 0x20 CORE_0_RCD_PDEBUGSP reg_core_0_rcd_pdebugsp 0 32 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_0 ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG 0x50 0x20 CORE_0_IRAM0_RECORDING_ADDR_0 reg_core_0_iram0_recording_addr_0 0 24 read-only CORE_0_IRAM0_RECORDING_WR_0 reg_core_0_iram0_recording_wr_0 24 1 read-only CORE_0_IRAM0_RECORDING_LOADSTORE_0 reg_core_0_iram0_recording_loadstore_0 25 1 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_1 ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG 0x54 0x20 CORE_0_IRAM0_RECORDING_ADDR_1 reg_core_0_iram0_recording_addr_1 0 24 read-only CORE_0_IRAM0_RECORDING_WR_1 reg_core_0_iram0_recording_wr_1 24 1 read-only CORE_0_IRAM0_RECORDING_LOADSTORE_1 reg_core_0_iram0_recording_loadstore_1 25 1 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_0 ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG 0x58 0x20 CORE_0_DRAM0_RECORDING_ADDR_0 reg_core_0_dram0_recording_addr_0 0 24 read-only CORE_0_DRAM0_RECORDING_WR_0 reg_core_0_dram0_recording_wr_0 24 1 read-only CORE_0_DRAM0_RECORDING_BYTEEN_0 reg_core_0_dram0_recording_byteen_0 25 4 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_1 ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG 0x5C 0x20 CORE_0_DRAM0_RECORDING_PC_0 reg_core_0_dram0_recording_pc_0 0 32 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_2 ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG 0x60 0x20 CORE_0_DRAM0_RECORDING_ADDR_1 reg_core_0_dram0_recording_addr_1 0 24 read-only CORE_0_DRAM0_RECORDING_WR_1 reg_core_0_dram0_recording_wr_1 24 1 read-only CORE_0_DRAM0_RECORDING_BYTEEN_1 reg_core_0_dram0_recording_byteen_1 25 4 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_3 ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG 0x64 0x20 CORE_0_DRAM0_RECORDING_PC_1 reg_core_0_dram0_recording_pc_1 0 32 read-only CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG 0x68 0x20 CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 reg_core_x_iram0_dram0_limit_cycle_0 0 20 read-write CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG 0x6C 0x20 CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 reg_core_x_iram0_dram0_limit_cycle_1 0 20 read-write LOG_SETTING ASSIST_DEBUG_LOG_SETTING 0x70 0x20 0x00000080 LOG_ENA reg_log_ena 0 3 read-write LOG_MODE reg_log_mode 3 4 read-write LOG_MEM_LOOP_ENABLE reg_log_mem_loop_enable 7 1 read-write LOG_DATA_0 ASSIST_DEBUG_LOG_DATA_0_REG 0x74 0x20 LOG_DATA_0 reg_log_data_0 0 32 read-write LOG_DATA_MASK ASSIST_DEBUG_LOG_DATA_MASK_REG 0x78 0x20 LOG_DATA_SIZE reg_log_data_size 0 16 read-write LOG_MIN ASSIST_DEBUG_LOG_MIN_REG 0x7C 0x20 LOG_MIN reg_log_min 0 32 read-write LOG_MAX ASSIST_DEBUG_LOG_MAX_REG 0x80 0x20 LOG_MAX reg_log_max 0 32 read-write LOG_MEM_START ASSIST_DEBUG_LOG_MEM_START_REG 0x84 0x20 LOG_MEM_START reg_log_mem_start 0 32 read-write LOG_MEM_END ASSIST_DEBUG_LOG_MEM_END_REG 0x88 0x20 LOG_MEM_END reg_log_mem_end 0 32 read-write LOG_MEM_WRITING_ADDR ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG 0x8C 0x20 LOG_MEM_WRITING_ADDR reg_log_mem_writing_addr 0 32 read-only LOG_MEM_FULL_FLAG ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG 0x90 0x20 LOG_MEM_FULL_FLAG reg_log_mem_full_flag 0 1 read-only CLR_LOG_MEM_FULL_FLAG reg_clr_log_mem_full_flag 1 1 read-write C0RE_0_LASTPC_BEFORE_EXCEPTION ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION 0x94 0x20 CORE_0_LASTPC_BEFORE_EXC reg_core_0_lastpc_before_exc 0 32 read-only C0RE_0_DEBUG_MODE ASSIST_DEBUG_C0RE_0_DEBUG_MODE 0x98 0x20 CORE_0_DEBUG_MODE reg_core_0_debug_mode 0 1 read-only CORE_0_DEBUG_MODULE_ACTIVE reg_core_0_debug_module_active 1 1 read-only DATE ASSIST_DEBUG_DATE_REG 0x1FC 0x20 0x02008010 ASSIST_DEBUG_DATE reg_assist_debug_date 0 28 read-write DMA DMA (Direct Memory Access) Controller DMA 0x6003F000 0x0 0x174 registers DMA_CH0 44 DMA_CH1 45 DMA_CH2 46 INT_RAW_CH0 DMA_INT_RAW_CH0_REG. 0x0 0x20 IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-only IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-only IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 read-only OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 read-only OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 read-only IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 read-only OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 read-only IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 read-only OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 read-only INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 read-only INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 read-only OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 read-only OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 read-only INT_ST_CH0 DMA_INT_ST_CH0_REG. 0x4 0x20 IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-only INT_ENA_CH0 DMA_INT_ENA_CH0_REG. 0x8 0x20 IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-write INT_CLR_CH0 DMA_INT_CLR_CH0_REG. 0xC 0x20 IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 write-only INT_RAW_CH1 DMA_INT_RAW_CH1_REG. 0x10 0x20 IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. 0 1 read-only IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-only IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved. 2 1 read-only OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1. 3 1 read-only OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1. 4 1 read-only IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 5 1 read-only OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1. 6 1 read-only IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1. 7 1 read-only OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1. 8 1 read-only INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow. 9 1 read-only INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow. 10 1 read-only OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow. 11 1 read-only OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow. 12 1 read-only INT_ST_CH1 DMA_INT_ST_CH1_REG. 0x14 0x20 IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-only INT_ENA_CH1 DMA_INT_ENA_CH1_REG. 0x18 0x20 IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-write INT_CLR_CH1 DMA_INT_CLR_CH1_REG. 0x1C 0x20 IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 write-only INT_RAW_CH2 DMA_INT_RAW_CH2_REG. 0x20 0x20 IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. 0 1 read-only IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2. 1 1 read-only IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved. 2 1 read-only OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2. 3 1 read-only OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2. 4 1 read-only IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2. 5 1 read-only OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2. 6 1 read-only IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2. 7 1 read-only OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2. 8 1 read-only INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow. 9 1 read-only INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow. 10 1 read-only OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow. 11 1 read-only OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow. 12 1 read-only INT_ST_CH2 DMA_INT_ST_CH2_REG. 0x24 0x20 IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-only INT_ENA_CH2 DMA_INT_ENA_CH2_REG. 0x28 0x20 IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-write INT_CLR_CH2 DMA_INT_CLR_CH2_REG. 0x2C 0x20 IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 write-only AHB_TEST DMA_AHB_TEST_REG. 0x40 0x20 AHB_TESTMODE reserved 0 3 read-write AHB_TESTADDR reserved 4 2 read-write MISC_CONF DMA_MISC_CONF_REG. 0x44 0x20 AHBM_RST_INTER Set this bit, then clear this bit to reset the internal ahb FSM. 0 1 read-write ARB_PRI_DIS Set this bit to disable priority arbitration function. 2 1 read-write CLK_EN reg_clk_en 3 1 read-write DATE DMA_DATE_REG. 0x48 0x20 0x02008250 DATE register version. 0 32 read-write IN_CONF0_CH0 DMA_IN_CONF0_CH0_REG. 0x70 0x20 IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write IN_LOOP_TEST reserved 1 1 read-write INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 read-write IN_CONF1_CH0 DMA_IN_CONF1_CH0_REG. 0x74 0x20 IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write INFIFO_STATUS_CH0 DMA_INFIFO_STATUS_CH0_REG. 0x78 0x20 0x07800003 INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only IN_REMAIN_UNDER_1B reserved 23 1 read-only IN_REMAIN_UNDER_2B reserved 24 1 read-only IN_REMAIN_UNDER_3B reserved 25 1 read-only IN_REMAIN_UNDER_4B reserved 26 1 read-only IN_BUF_HUNGRY reserved 27 1 read-only IN_POP_CH0 DMA_IN_POP_CH0_REG. 0x7C 0x20 0x00000800 INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 read-write IN_LINK_CH0 DMA_IN_LINK_CH0_REG. 0x80 0x20 0x01100000 INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 read-only IN_STATE_CH0 DMA_IN_STATE_CH0_REG. 0x84 0x20 INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only IN_DSCR_STATE reserved 18 2 read-only IN_STATE reserved 20 3 read-only IN_SUC_EOF_DES_ADDR_CH0 DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. 0x88 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only IN_ERR_EOF_DES_ADDR_CH0 DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. 0x8C 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 read-only IN_DSCR_CH0 DMA_IN_DSCR_CH0_REG. 0x90 0x20 INLINK_DSCR The address of the current inlink descriptor x. 0 32 read-only IN_DSCR_BF0_CH0 DMA_IN_DSCR_BF0_CH0_REG. 0x94 0x20 INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 read-only IN_DSCR_BF1_CH0 DMA_IN_DSCR_BF1_CH0_REG. 0x98 0x20 INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only IN_PRI_CH0 DMA_IN_PRI_CH0_REG. 0x9C 0x20 RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 read-write IN_PERI_SEL_CH0 DMA_IN_PERI_SEL_CH0_REG. 0xA0 0x20 0x0000003F PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write OUT_CONF0_CH0 DMA_OUT_CONF0_CH0_REG. 0xD0 0x20 0x00000008 OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write OUT_LOOP_TEST reserved 1 1 read-write OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 read-write OUT_CONF1_CH0 DMA_OUT_CONF1_CH0_REG. 0xD4 0x20 OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write OUTFIFO_STATUS_CH0 DMA_OUTFIFO_STATUS_CH0_REG. 0xD8 0x20 0x07800002 OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only OUT_REMAIN_UNDER_1B reserved 23 1 read-only OUT_REMAIN_UNDER_2B reserved 24 1 read-only OUT_REMAIN_UNDER_3B reserved 25 1 read-only OUT_REMAIN_UNDER_4B reserved 26 1 read-only OUT_PUSH_CH0 DMA_OUT_PUSH_CH0_REG. 0xDC 0x20 OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 read-write OUT_LINK_CH0 DMA_OUT_LINK_CH0_REG. 0xE0 0x20 0x00800000 OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 read-only OUT_STATE_CH0 DMA_OUT_STATE_CH0_REG. 0xE4 0x20 OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only OUT_DSCR_STATE reserved 18 2 read-only OUT_STATE reserved 20 3 read-only OUT_EOF_DES_ADDR_CH0 DMA_OUT_EOF_DES_ADDR_CH0_REG. 0xE8 0x20 OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only OUT_EOF_BFR_DES_ADDR_CH0 DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. 0xEC 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 read-only OUT_DSCR_CH0 DMA_OUT_DSCR_CH0_REG. 0xF0 0x20 OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 read-only OUT_DSCR_BF0_CH0 DMA_OUT_DSCR_BF0_CH0_REG. 0xF4 0x20 OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 read-only OUT_DSCR_BF1_CH0 DMA_OUT_DSCR_BF1_CH0_REG. 0xF8 0x20 OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only OUT_PRI_CH0 DMA_OUT_PRI_CH0_REG. 0xFC 0x20 TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 read-write OUT_PERI_SEL_CH0 DMA_OUT_PERI_SEL_CH0_REG. 0x100 0x20 0x0000003F PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write IN_CONF0_CH1 DMA_IN_CONF0_CH1_REG. 0x130 0x20 IN_RST This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. 0 1 read-write IN_LOOP_TEST reserved 1 1 read-write INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM. 2 1 read-write IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM. 3 1 read-write MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 read-write IN_CONF1_CH1 DMA_IN_CONF1_CH1_REG. 0x134 0x20 IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write INFIFO_STATUS_CH1 DMA_INFIFO_STATUS_CH1_REG. 0x138 0x20 0x07800003 INFIFO_FULL L1 Rx FIFO full signal for Rx channel 1. 0 1 read-only INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 1. 1 1 read-only INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. 2 6 read-only IN_REMAIN_UNDER_1B reserved 23 1 read-only IN_REMAIN_UNDER_2B reserved 24 1 read-only IN_REMAIN_UNDER_3B reserved 25 1 read-only IN_REMAIN_UNDER_4B reserved 26 1 read-only IN_BUF_HUNGRY reserved 27 1 read-only IN_POP_CH1 DMA_IN_POP_CH1_REG. 0x13C 0x20 0x00000800 INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 read-write IN_LINK_CH1 DMA_IN_LINK_CH1_REG. 0x140 0x20 0x01100000 INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 read-only IN_STATE_CH1 DMA_IN_STATE_CH1_REG. 0x144 0x20 INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only IN_DSCR_STATE reserved 18 2 read-only IN_STATE reserved 20 3 read-only IN_SUC_EOF_DES_ADDR_CH1 DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. 0x148 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only IN_ERR_EOF_DES_ADDR_CH1 DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. 0x14C 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 read-only IN_DSCR_CH1 DMA_IN_DSCR_CH1_REG. 0x150 0x20 INLINK_DSCR The address of the current inlink descriptor x. 0 32 read-only IN_DSCR_BF0_CH1 DMA_IN_DSCR_BF0_CH1_REG. 0x154 0x20 INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 read-only IN_DSCR_BF1_CH1 DMA_IN_DSCR_BF1_CH1_REG. 0x158 0x20 INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only IN_PRI_CH1 DMA_IN_PRI_CH1_REG. 0x15C 0x20 RX_PRI The priority of Rx channel 1. The larger of the value, the higher of the priority. 0 4 read-write IN_PERI_SEL_CH1 DMA_IN_PERI_SEL_CH1_REG. 0x160 0x20 0x0000003F PERI_IN_SEL This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write OUT_CONF0_CH1 DMA_OUT_CONF0_CH1_REG. 0x190 0x20 0x00000008 OUT_RST This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. 0 1 read-write OUT_LOOP_TEST reserved 1 1 read-write OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. 4 1 read-write OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. 5 1 read-write OUT_CONF1_CH1 DMA_OUT_CONF1_CH1_REG. 0x194 0x20 OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write OUTFIFO_STATUS_CH1 DMA_OUTFIFO_STATUS_CH1_REG. 0x198 0x20 0x07800002 OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 1. 0 1 read-only OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 1. 1 1 read-only OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. 2 6 read-only OUT_REMAIN_UNDER_1B reserved 23 1 read-only OUT_REMAIN_UNDER_2B reserved 24 1 read-only OUT_REMAIN_UNDER_3B reserved 25 1 read-only OUT_REMAIN_UNDER_4B reserved 26 1 read-only OUT_PUSH_CH1 DMA_OUT_PUSH_CH1_REG. 0x19C 0x20 OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 read-write OUT_LINK_CH1 DMA_OUT_LINK_CH1_REG. 0x1A0 0x20 0x00800000 OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 read-only OUT_STATE_CH1 DMA_OUT_STATE_CH1_REG. 0x1A4 0x20 OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only OUT_DSCR_STATE reserved 18 2 read-only OUT_STATE reserved 20 3 read-only OUT_EOF_DES_ADDR_CH1 DMA_OUT_EOF_DES_ADDR_CH1_REG. 0x1A8 0x20 OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only OUT_EOF_BFR_DES_ADDR_CH1 DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. 0x1AC 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 read-only OUT_DSCR_CH1 DMA_OUT_DSCR_CH1_REG. 0x1B0 0x20 OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 read-only OUT_DSCR_BF0_CH1 DMA_OUT_DSCR_BF0_CH1_REG. 0x1B4 0x20 OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 read-only OUT_DSCR_BF1_CH1 DMA_OUT_DSCR_BF1_CH1_REG. 0x1B8 0x20 OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only OUT_PRI_CH1 DMA_OUT_PRI_CH1_REG. 0x1BC 0x20 TX_PRI The priority of Tx channel 1. The larger of the value, the higher of the priority. 0 4 read-write OUT_PERI_SEL_CH1 DMA_OUT_PERI_SEL_CH1_REG. 0x1C0 0x20 0x0000003F PERI_OUT_SEL This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write IN_CONF0_CH2 DMA_IN_CONF0_CH2_REG. 0x1F0 0x20 IN_RST This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. 0 1 read-write IN_LOOP_TEST reserved 1 1 read-write INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM. 2 1 read-write IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM. 3 1 read-write MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 read-write IN_CONF1_CH2 DMA_IN_CONF1_CH2_REG. 0x1F4 0x20 IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write INFIFO_STATUS_CH2 DMA_INFIFO_STATUS_CH2_REG. 0x1F8 0x20 0x07800003 INFIFO_FULL L1 Rx FIFO full signal for Rx channel 2. 0 1 read-only INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 2. 1 1 read-only INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. 2 6 read-only IN_REMAIN_UNDER_1B reserved 23 1 read-only IN_REMAIN_UNDER_2B reserved 24 1 read-only IN_REMAIN_UNDER_3B reserved 25 1 read-only IN_REMAIN_UNDER_4B reserved 26 1 read-only IN_BUF_HUNGRY reserved 27 1 read-only IN_POP_CH2 DMA_IN_POP_CH2_REG. 0x1FC 0x20 0x00000800 INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 read-write IN_LINK_CH2 DMA_IN_LINK_CH2_REG. 0x200 0x20 0x01100000 INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 read-only IN_STATE_CH2 DMA_IN_STATE_CH2_REG. 0x204 0x20 INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only IN_DSCR_STATE reserved 18 2 read-only IN_STATE reserved 20 3 read-only IN_SUC_EOF_DES_ADDR_CH2 DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. 0x208 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only IN_ERR_EOF_DES_ADDR_CH2 DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. 0x20C 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 read-only IN_DSCR_CH2 DMA_IN_DSCR_CH2_REG. 0x210 0x20 INLINK_DSCR The address of the current inlink descriptor x. 0 32 read-only IN_DSCR_BF0_CH2 DMA_IN_DSCR_BF0_CH2_REG. 0x214 0x20 INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 read-only IN_DSCR_BF1_CH2 DMA_IN_DSCR_BF1_CH2_REG. 0x218 0x20 INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only IN_PRI_CH2 DMA_IN_PRI_CH2_REG. 0x21C 0x20 RX_PRI The priority of Rx channel 2. The larger of the value, the higher of the priority. 0 4 read-write IN_PERI_SEL_CH2 DMA_IN_PERI_SEL_CH2_REG. 0x220 0x20 0x0000003F PERI_IN_SEL This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write OUT_CONF0_CH2 DMA_OUT_CONF0_CH2_REG. 0x250 0x20 0x00000008 OUT_RST This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. 0 1 read-write OUT_LOOP_TEST reserved 1 1 read-write OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM. 4 1 read-write OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM. 5 1 read-write OUT_CONF1_CH2 DMA_OUT_CONF1_CH2_REG. 0x254 0x20 OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write OUTFIFO_STATUS_CH2 DMA_OUTFIFO_STATUS_CH2_REG. 0x258 0x20 0x07800002 OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 2. 0 1 read-only OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 2. 1 1 read-only OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. 2 6 read-only OUT_REMAIN_UNDER_1B reserved 23 1 read-only OUT_REMAIN_UNDER_2B reserved 24 1 read-only OUT_REMAIN_UNDER_3B reserved 25 1 read-only OUT_REMAIN_UNDER_4B reserved 26 1 read-only OUT_PUSH_CH2 DMA_OUT_PUSH_CH2_REG. 0x25C 0x20 OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 read-write OUT_LINK_CH2 DMA_OUT_LINK_CH2_REG. 0x260 0x20 0x00800000 OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 read-only OUT_STATE_CH2 DMA_OUT_STATE_CH2_REG. 0x264 0x20 OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only OUT_DSCR_STATE reserved 18 2 read-only OUT_STATE reserved 20 3 read-only OUT_EOF_DES_ADDR_CH2 DMA_OUT_EOF_DES_ADDR_CH2_REG. 0x268 0x20 OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only OUT_EOF_BFR_DES_ADDR_CH2 DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. 0x26C 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 read-only OUT_DSCR_CH2 DMA_OUT_DSCR_CH2_REG. 0x270 0x20 OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 read-only OUT_DSCR_BF0_CH2 DMA_OUT_DSCR_BF0_CH2_REG. 0x274 0x20 OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 read-only OUT_DSCR_BF1_CH2 DMA_OUT_DSCR_BF1_CH2_REG. 0x278 0x20 OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only OUT_PRI_CH2 DMA_OUT_PRI_CH2_REG. 0x27C 0x20 TX_PRI The priority of Tx channel 2. The larger of the value, the higher of the priority. 0 4 read-write OUT_PERI_SEL_CH2 DMA_OUT_PERI_SEL_CH2_REG. 0x280 0x20 0x0000003F PERI_OUT_SEL This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write DS Digital Signature DS 0x6003D000 0x0 0x108C registers 512 0x1 Y_MEM[%s] memory that stores Y 0x0 0x8 512 0x1 M_MEM[%s] memory that stores M 0x200 0x8 512 0x1 RB_MEM[%s] memory that stores Rb 0x400 0x8 48 0x1 BOX_MEM[%s] memory that stores BOX 0x600 0x8 512 0x1 X_MEM[%s] memory that stores X 0x800 0x8 512 0x1 Z_MEM[%s] memory that stores Z 0xA00 0x8 SET_START DS start control register 0xE00 0x20 SET_START set this bit to start DS operation. 0 1 write-only SET_CONTINUE DS continue control register 0xE04 0x20 SET_CONTINUE set this bit to continue DS operation. 0 1 write-only SET_FINISH DS finish control register 0xE08 0x20 SET_FINISH Set this bit to finish DS process. 0 1 write-only QUERY_BUSY DS query busy register 0xE0C 0x20 QUERY_BUSY digital signature state. 1'b0: idle, 1'b1: busy 0 1 read-only QUERY_KEY_WRONG DS query key-wrong counter register 0xE10 0x20 QUERY_KEY_WRONG digital signature key wrong counter 0 4 read-only QUERY_CHECK DS query check result register 0xE14 0x20 MD_ERROR MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail 0 1 read-only PADDING_BAD padding checkout result. 1'b0: a good padding, 1'b1: a bad padding 1 1 read-only DATE DS version control register 0xE20 0x20 0x20200618 DATE ds version information 0 30 read-write EFUSE eFuse Controller EFUSE 0x60008800 0x0 0x1CC registers EFUSE 24 PGM_DATA0 Register 0 that stores data to be programmed. 0x0 0x20 PGM_DATA_0 The content of the 0th 32-bit data to be programmed. 0 32 read-write PGM_DATA1 Register 1 that stores data to be programmed. 0x4 0x20 PGM_DATA_1 The content of the 1st 32-bit data to be programmed. 0 32 read-write PGM_DATA2 Register 2 that stores data to be programmed. 0x8 0x20 PGM_DATA_2 The content of the 2nd 32-bit data to be programmed. 0 32 read-write PGM_DATA3 Register 3 that stores data to be programmed. 0xC 0x20 PGM_DATA_3 The content of the 3rd 32-bit data to be programmed. 0 32 read-write PGM_DATA4 Register 4 that stores data to be programmed. 0x10 0x20 PGM_DATA_4 The content of the 4th 32-bit data to be programmed. 0 32 read-write PGM_DATA5 Register 5 that stores data to be programmed. 0x14 0x20 PGM_DATA_5 The content of the 5th 32-bit data to be programmed. 0 32 read-write PGM_DATA6 Register 6 that stores data to be programmed. 0x18 0x20 PGM_DATA_6 The content of the 6th 32-bit data to be programmed. 0 32 read-write PGM_DATA7 Register 7 that stores data to be programmed. 0x1C 0x20 PGM_DATA_7 The content of the 7th 32-bit data to be programmed. 0 32 read-write PGM_CHECK_VALUE0 Register 0 that stores the RS code to be programmed. 0x20 0x20 PGM_RS_DATA_0 The content of the 0th 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE1 Register 1 that stores the RS code to be programmed. 0x24 0x20 PGM_RS_DATA_1 The content of the 1st 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE2 Register 2 that stores the RS code to be programmed. 0x28 0x20 PGM_RS_DATA_2 The content of the 2nd 32-bit RS code to be programmed. 0 32 read-write RD_WR_DIS BLOCK0 data register 0. 0x2C 0x20 WR_DIS Disable programming of individual eFuses. 0 32 read-only RD_REPEAT_DATA0 BLOCK0 data register 1. 0x30 0x20 RD_DIS Set this bit to disable reading from BlOCK4-10. 0 7 read-only DIS_RTC_RAM_BOOT Set this bit to disable boot from RTC RAM. 7 1 read-only DIS_ICACHE Set this bit to disable Icache. 8 1 read-only DIS_USB_JTAG Set this bit to disable function of usb switch to jtag in module of usb device. 9 1 read-only DIS_DOWNLOAD_ICACHE Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7). 10 1 read-only DIS_USB_DEVICE Set this bit to disable usb device. 11 1 read-only DIS_FORCE_DOWNLOAD Set this bit to disable the function that forces chip into download mode. 12 1 read-only RPT4_RESERVED6 Reserved (used for four backups method). 13 1 read-only DIS_CAN Set this bit to disable CAN function. 14 1 read-only JTAG_SEL_ENABLE Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. 15 1 read-only SOFT_DIS_JTAG Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. 16 3 read-only DIS_PAD_JTAG Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. 19 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT Set this bit to disable flash encryption when in download boot modes. 20 1 read-only USB_DREFH Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. 21 2 read-only USB_DREFL Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. 23 2 read-only USB_EXCHG_PINS Set this bit to exchange USB D+ and D- pins. 25 1 read-only VDD_SPI_AS_GPIO Set this bit to vdd spi pin function as gpio. 26 1 read-only BTLC_GPIO_ENABLE Enable btlc gpio. 27 2 read-only POWERGLITCH_EN Set this bit to enable power glitch function. 29 1 read-only POWER_GLITCH_DSENSE Sample delay configuration of power glitch. 30 2 read-only RD_REPEAT_DATA1 BLOCK0 data register 2. 0x34 0x20 RPT4_RESERVED2 Reserved (used for four backups method). 0 16 read-only WDT_DELAY_SEL Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. 16 2 read-only SPI_BOOT_CRYPT_CNT Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. 18 3 read-only SECURE_BOOT_KEY_REVOKE0 Set this bit to enable revoking first secure boot key. 21 1 read-only SECURE_BOOT_KEY_REVOKE1 Set this bit to enable revoking second secure boot key. 22 1 read-only SECURE_BOOT_KEY_REVOKE2 Set this bit to enable revoking third secure boot key. 23 1 read-only KEY_PURPOSE_0 Purpose of Key0. 24 4 read-only KEY_PURPOSE_1 Purpose of Key1. 28 4 read-only RD_REPEAT_DATA2 BLOCK0 data register 3. 0x38 0x20 KEY_PURPOSE_2 Purpose of Key2. 0 4 read-only KEY_PURPOSE_3 Purpose of Key3. 4 4 read-only KEY_PURPOSE_4 Purpose of Key4. 8 4 read-only KEY_PURPOSE_5 Purpose of Key5. 12 4 read-only RPT4_RESERVED3 Reserved (used for four backups method). 16 4 read-only SECURE_BOOT_EN Set this bit to enable secure boot. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE Set this bit to enable revoking aggressive secure boot. 21 1 read-only RPT4_RESERVED0 Reserved (used for four backups method). 22 6 read-only FLASH_TPUW Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value. 28 4 read-only RD_REPEAT_DATA3 BLOCK0 data register 4. 0x3C 0x20 DIS_DOWNLOAD_MODE Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). 0 1 read-only DIS_LEGACY_SPI_BOOT Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). 1 1 read-only UART_PRINT_CHANNEL Selectes the default UART print channel. 0: UART0. 1: UART1. 2 1 read-only FLASH_ECC_MODE Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode. 3 1 read-only DIS_USB_DOWNLOAD_MODE Set this bit to disable UART download mode through USB. 4 1 read-only ENABLE_SECURITY_DOWNLOAD Set this bit to enable secure UART download mode. 5 1 read-only UART_PRINT_CONTROL Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. 6 2 read-only PIN_POWER_SELECTION GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. 8 1 read-only FLASH_TYPE Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. 9 1 read-only FLASH_PAGE_SIZE Set Flash page size. 10 2 read-only FLASH_ECC_EN Set 1 to enable ECC for flash boot. 12 1 read-only FORCE_SEND_RESUME Set this bit to force ROM code to send a resume command during SPI boot. 13 1 read-only SECURE_VERSION Secure version (used by ESP-IDF anti-rollback feature). 14 16 read-only RPT4_RESERVED1 Reserved (used for four backups method). 30 2 read-only RD_REPEAT_DATA4 BLOCK0 data register 5. 0x40 0x20 RPT4_RESERVED4 Reserved (used for four backups method). 0 24 read-only RD_MAC_SPI_SYS_0 BLOCK1 data register 0. 0x44 0x20 MAC_0 Stores the low 32 bits of MAC address. 0 32 read-only RD_MAC_SPI_SYS_1 BLOCK1 data register 1. 0x48 0x20 MAC_1 Stores the high 16 bits of MAC address. 0 16 read-only SPI_PAD_CONF_0 Stores the zeroth part of SPI_PAD_CONF. 16 16 read-only RD_MAC_SPI_SYS_2 BLOCK1 data register 2. 0x4C 0x20 SPI_PAD_CONF_1 Stores the first part of SPI_PAD_CONF. 0 32 read-only RD_MAC_SPI_SYS_3 BLOCK1 data register 3. 0x50 0x20 SPI_PAD_CONF_2 Stores the second part of SPI_PAD_CONF. 0 18 read-only SYS_DATA_PART0_0 Stores the fist 14 bits of the zeroth part of system data. 18 14 read-only RD_MAC_SPI_SYS_4 BLOCK1 data register 4. 0x54 0x20 SYS_DATA_PART0_1 Stores the fist 32 bits of the zeroth part of system data. 0 32 read-only RD_MAC_SPI_SYS_5 BLOCK1 data register 5. 0x58 0x20 SYS_DATA_PART0_2 Stores the second 32 bits of the zeroth part of system data. 0 32 read-only RD_SYS_PART1_DATA0 Register 0 of BLOCK2 (system). 0x5C 0x20 SYS_DATA_PART1_0 Stores the zeroth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA1 Register 1 of BLOCK2 (system). 0x60 0x20 SYS_DATA_PART1_1 Stores the first 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA2 Register 2 of BLOCK2 (system). 0x64 0x20 SYS_DATA_PART1_2 Stores the second 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA3 Register 3 of BLOCK2 (system). 0x68 0x20 SYS_DATA_PART1_3 Stores the third 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA4 Register 4 of BLOCK2 (system). 0x6C 0x20 SYS_DATA_PART1_4 Stores the fourth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA5 Register 5 of BLOCK2 (system). 0x70 0x20 SYS_DATA_PART1_5 Stores the fifth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA6 Register 6 of BLOCK2 (system). 0x74 0x20 SYS_DATA_PART1_6 Stores the sixth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA7 Register 7 of BLOCK2 (system). 0x78 0x20 SYS_DATA_PART1_7 Stores the seventh 32 bits of the first part of system data. 0 32 read-only RD_USR_DATA0 Register 0 of BLOCK3 (user). 0x7C 0x20 USR_DATA0 Stores the zeroth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA1 Register 1 of BLOCK3 (user). 0x80 0x20 USR_DATA1 Stores the first 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA2 Register 2 of BLOCK3 (user). 0x84 0x20 USR_DATA2 Stores the second 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA3 Register 3 of BLOCK3 (user). 0x88 0x20 USR_DATA3 Stores the third 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA4 Register 4 of BLOCK3 (user). 0x8C 0x20 USR_DATA4 Stores the fourth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA5 Register 5 of BLOCK3 (user). 0x90 0x20 USR_DATA5 Stores the fifth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA6 Register 6 of BLOCK3 (user). 0x94 0x20 USR_DATA6 Stores the sixth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA7 Register 7 of BLOCK3 (user). 0x98 0x20 USR_DATA7 Stores the seventh 32 bits of BLOCK3 (user). 0 32 read-only RD_KEY0_DATA0 Register 0 of BLOCK4 (KEY0). 0x9C 0x20 KEY0_DATA0 Stores the zeroth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA1 Register 1 of BLOCK4 (KEY0). 0xA0 0x20 KEY0_DATA1 Stores the first 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA2 Register 2 of BLOCK4 (KEY0). 0xA4 0x20 KEY0_DATA2 Stores the second 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA3 Register 3 of BLOCK4 (KEY0). 0xA8 0x20 KEY0_DATA3 Stores the third 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA4 Register 4 of BLOCK4 (KEY0). 0xAC 0x20 KEY0_DATA4 Stores the fourth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA5 Register 5 of BLOCK4 (KEY0). 0xB0 0x20 KEY0_DATA5 Stores the fifth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA6 Register 6 of BLOCK4 (KEY0). 0xB4 0x20 KEY0_DATA6 Stores the sixth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA7 Register 7 of BLOCK4 (KEY0). 0xB8 0x20 KEY0_DATA7 Stores the seventh 32 bits of KEY0. 0 32 read-only RD_KEY1_DATA0 Register 0 of BLOCK5 (KEY1). 0xBC 0x20 KEY1_DATA0 Stores the zeroth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA1 Register 1 of BLOCK5 (KEY1). 0xC0 0x20 KEY1_DATA1 Stores the first 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA2 Register 2 of BLOCK5 (KEY1). 0xC4 0x20 KEY1_DATA2 Stores the second 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA3 Register 3 of BLOCK5 (KEY1). 0xC8 0x20 KEY1_DATA3 Stores the third 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA4 Register 4 of BLOCK5 (KEY1). 0xCC 0x20 KEY1_DATA4 Stores the fourth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA5 Register 5 of BLOCK5 (KEY1). 0xD0 0x20 KEY1_DATA5 Stores the fifth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA6 Register 6 of BLOCK5 (KEY1). 0xD4 0x20 KEY1_DATA6 Stores the sixth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA7 Register 7 of BLOCK5 (KEY1). 0xD8 0x20 KEY1_DATA7 Stores the seventh 32 bits of KEY1. 0 32 read-only RD_KEY2_DATA0 Register 0 of BLOCK6 (KEY2). 0xDC 0x20 KEY2_DATA0 Stores the zeroth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA1 Register 1 of BLOCK6 (KEY2). 0xE0 0x20 KEY2_DATA1 Stores the first 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA2 Register 2 of BLOCK6 (KEY2). 0xE4 0x20 KEY2_DATA2 Stores the second 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA3 Register 3 of BLOCK6 (KEY2). 0xE8 0x20 KEY2_DATA3 Stores the third 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA4 Register 4 of BLOCK6 (KEY2). 0xEC 0x20 KEY2_DATA4 Stores the fourth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA5 Register 5 of BLOCK6 (KEY2). 0xF0 0x20 KEY2_DATA5 Stores the fifth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA6 Register 6 of BLOCK6 (KEY2). 0xF4 0x20 KEY2_DATA6 Stores the sixth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA7 Register 7 of BLOCK6 (KEY2). 0xF8 0x20 KEY2_DATA7 Stores the seventh 32 bits of KEY2. 0 32 read-only RD_KEY3_DATA0 Register 0 of BLOCK7 (KEY3). 0xFC 0x20 KEY3_DATA0 Stores the zeroth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA1 Register 1 of BLOCK7 (KEY3). 0x100 0x20 KEY3_DATA1 Stores the first 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA2 Register 2 of BLOCK7 (KEY3). 0x104 0x20 KEY3_DATA2 Stores the second 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA3 Register 3 of BLOCK7 (KEY3). 0x108 0x20 KEY3_DATA3 Stores the third 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA4 Register 4 of BLOCK7 (KEY3). 0x10C 0x20 KEY3_DATA4 Stores the fourth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA5 Register 5 of BLOCK7 (KEY3). 0x110 0x20 KEY3_DATA5 Stores the fifth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA6 Register 6 of BLOCK7 (KEY3). 0x114 0x20 KEY3_DATA6 Stores the sixth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA7 Register 7 of BLOCK7 (KEY3). 0x118 0x20 KEY3_DATA7 Stores the seventh 32 bits of KEY3. 0 32 read-only RD_KEY4_DATA0 Register 0 of BLOCK8 (KEY4). 0x11C 0x20 KEY4_DATA0 Stores the zeroth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA1 Register 1 of BLOCK8 (KEY4). 0x120 0x20 KEY4_DATA1 Stores the first 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA2 Register 2 of BLOCK8 (KEY4). 0x124 0x20 KEY4_DATA2 Stores the second 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA3 Register 3 of BLOCK8 (KEY4). 0x128 0x20 KEY4_DATA3 Stores the third 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA4 Register 4 of BLOCK8 (KEY4). 0x12C 0x20 KEY4_DATA4 Stores the fourth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA5 Register 5 of BLOCK8 (KEY4). 0x130 0x20 KEY4_DATA5 Stores the fifth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA6 Register 6 of BLOCK8 (KEY4). 0x134 0x20 KEY4_DATA6 Stores the sixth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA7 Register 7 of BLOCK8 (KEY4). 0x138 0x20 KEY4_DATA7 Stores the seventh 32 bits of KEY4. 0 32 read-only RD_KEY5_DATA0 Register 0 of BLOCK9 (KEY5). 0x13C 0x20 KEY5_DATA0 Stores the zeroth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA1 Register 1 of BLOCK9 (KEY5). 0x140 0x20 KEY5_DATA1 Stores the first 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA2 Register 2 of BLOCK9 (KEY5). 0x144 0x20 KEY5_DATA2 Stores the second 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA3 Register 3 of BLOCK9 (KEY5). 0x148 0x20 KEY5_DATA3 Stores the third 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA4 Register 4 of BLOCK9 (KEY5). 0x14C 0x20 KEY5_DATA4 Stores the fourth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA5 Register 5 of BLOCK9 (KEY5). 0x150 0x20 KEY5_DATA5 Stores the fifth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA6 Register 6 of BLOCK9 (KEY5). 0x154 0x20 KEY5_DATA6 Stores the sixth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA7 Register 7 of BLOCK9 (KEY5). 0x158 0x20 KEY5_DATA7 Stores the seventh 32 bits of KEY5. 0 32 read-only RD_SYS_PART2_DATA0 Register 0 of BLOCK10 (system). 0x15C 0x20 SYS_DATA_PART2_0 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA1 Register 1 of BLOCK9 (KEY5). 0x160 0x20 SYS_DATA_PART2_1 Stores the 1st 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA2 Register 2 of BLOCK10 (system). 0x164 0x20 SYS_DATA_PART2_2 Stores the 2nd 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA3 Register 3 of BLOCK10 (system). 0x168 0x20 SYS_DATA_PART2_3 Stores the 3rd 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA4 Register 4 of BLOCK10 (system). 0x16C 0x20 SYS_DATA_PART2_4 Stores the 4th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA5 Register 5 of BLOCK10 (system). 0x170 0x20 SYS_DATA_PART2_5 Stores the 5th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA6 Register 6 of BLOCK10 (system). 0x174 0x20 SYS_DATA_PART2_6 Stores the 6th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA7 Register 7 of BLOCK10 (system). 0x178 0x20 SYS_DATA_PART2_7 Stores the 7th 32 bits of the 2nd part of system data. 0 32 read-only RD_REPEAT_ERR0 Programming error record register 0 of BLOCK0. 0x17C 0x20 RD_DIS_ERR If any bit in RD_DIS is 1, then it indicates a programming error. 0 7 read-only DIS_RTC_RAM_BOOT_ERR If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. 7 1 read-only DIS_ICACHE_ERR If DIS_ICACHE is 1, then it indicates a programming error. 8 1 read-only DIS_USB_JTAG_ERR If DIS_USB_JTAG is 1, then it indicates a programming error. 9 1 read-only DIS_DOWNLOAD_ICACHE_ERR If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. 10 1 read-only DIS_USB_DEVICE_ERR If DIS_USB_DEVICE is 1, then it indicates a programming error. 11 1 read-only DIS_FORCE_DOWNLOAD_ERR If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. 12 1 read-only RPT4_RESERVED6_ERR Reserved. 13 1 read-only DIS_CAN_ERR If DIS_CAN is 1, then it indicates a programming error. 14 1 read-only JTAG_SEL_ENABLE_ERR If JTAG_SEL_ENABLE is 1, then it indicates a programming error. 15 1 read-only SOFT_DIS_JTAG_ERR If SOFT_DIS_JTAG is 1, then it indicates a programming error. 16 3 read-only DIS_PAD_JTAG_ERR If DIS_PAD_JTAG is 1, then it indicates a programming error. 19 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. 20 1 read-only USB_DREFH_ERR If any bit in USB_DREFH is 1, then it indicates a programming error. 21 2 read-only USB_DREFL_ERR If any bit in USB_DREFL is 1, then it indicates a programming error. 23 2 read-only USB_EXCHG_PINS_ERR If USB_EXCHG_PINS is 1, then it indicates a programming error. 25 1 read-only VDD_SPI_AS_GPIO_ERR If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. 26 1 read-only BTLC_GPIO_ENABLE_ERR If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. 27 2 read-only POWERGLITCH_EN_ERR If POWERGLITCH_EN is 1, then it indicates a programming error. 29 1 read-only POWER_GLITCH_DSENSE_ERR If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. 30 2 read-only RD_REPEAT_ERR1 Programming error record register 1 of BLOCK0. 0x180 0x20 RPT4_RESERVED2_ERR Reserved. 0 16 read-only WDT_DELAY_SEL_ERR If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. 16 2 read-only SPI_BOOT_CRYPT_CNT_ERR If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. 18 3 read-only SECURE_BOOT_KEY_REVOKE0_ERR If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. 21 1 read-only SECURE_BOOT_KEY_REVOKE1_ERR If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. 22 1 read-only SECURE_BOOT_KEY_REVOKE2_ERR If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. 23 1 read-only KEY_PURPOSE_0_ERR If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. 24 4 read-only KEY_PURPOSE_1_ERR If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. 28 4 read-only RD_REPEAT_ERR2 Programming error record register 2 of BLOCK0. 0x184 0x20 KEY_PURPOSE_2_ERR If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. 0 4 read-only KEY_PURPOSE_3_ERR If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. 4 4 read-only KEY_PURPOSE_4_ERR If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. 8 4 read-only KEY_PURPOSE_5_ERR If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. 12 4 read-only RPT4_RESERVED3_ERR Reserved. 16 4 read-only SECURE_BOOT_EN_ERR If SECURE_BOOT_EN is 1, then it indicates a programming error. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE_ERR If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. 21 1 read-only RPT4_RESERVED0_ERR Reserved. 22 6 read-only FLASH_TPUW_ERR If any bit in FLASH_TPUM is 1, then it indicates a programming error. 28 4 read-only RD_REPEAT_ERR3 Programming error record register 3 of BLOCK0. 0x188 0x20 DIS_DOWNLOAD_MODE_ERR If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. 0 1 read-only DIS_LEGACY_SPI_BOOT_ERR If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. 1 1 read-only UART_PRINT_CHANNEL_ERR If UART_PRINT_CHANNEL is 1, then it indicates a programming error. 2 1 read-only FLASH_ECC_MODE_ERR If FLASH_ECC_MODE is 1, then it indicates a programming error. 3 1 read-only DIS_USB_DOWNLOAD_MODE_ERR If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. 4 1 read-only ENABLE_SECURITY_DOWNLOAD_ERR If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. 5 1 read-only UART_PRINT_CONTROL_ERR If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. 6 2 read-only PIN_POWER_SELECTION_ERR If PIN_POWER_SELECTION is 1, then it indicates a programming error. 8 1 read-only FLASH_TYPE_ERR If FLASH_TYPE is 1, then it indicates a programming error. 9 1 read-only FLASH_PAGE_SIZE_ERR If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. 10 2 read-only FLASH_ECC_EN_ERR If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. 12 1 read-only FORCE_SEND_RESUME_ERR If FORCE_SEND_RESUME is 1, then it indicates a programming error. 13 1 read-only SECURE_VERSION_ERR If any bit in SECURE_VERSION is 1, then it indicates a programming error. 14 16 read-only RPT4_RESERVED1_ERR Reserved. 30 2 read-only RD_REPEAT_ERR4 Programming error record register 4 of BLOCK0. 0x190 0x20 RPT4_RESERVED4_ERR Reserved. 0 24 read-only RD_RS_ERR0 Programming error record register 0 of BLOCK1-10. 0x1C0 0x20 MAC_SPI_8M_ERR_NUM The value of this signal means the number of error bytes. 0 3 read-only MAC_SPI_8M_FAIL 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 3 1 read-only SYS_PART1_NUM The value of this signal means the number of error bytes. 4 3 read-only SYS_PART1_FAIL 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 7 1 read-only USR_DATA_ERR_NUM The value of this signal means the number of error bytes. 8 3 read-only USR_DATA_FAIL 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 11 1 read-only KEY0_ERR_NUM The value of this signal means the number of error bytes. 12 3 read-only KEY0_FAIL 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. 15 1 read-only KEY1_ERR_NUM The value of this signal means the number of error bytes. 16 3 read-only KEY1_FAIL 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. 19 1 read-only KEY2_ERR_NUM The value of this signal means the number of error bytes. 20 3 read-only KEY2_FAIL 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. 23 1 read-only KEY3_ERR_NUM The value of this signal means the number of error bytes. 24 3 read-only KEY3_FAIL 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. 27 1 read-only KEY4_ERR_NUM The value of this signal means the number of error bytes. 28 3 read-only KEY4_FAIL 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. 31 1 read-only RD_RS_ERR1 Programming error record register 1 of BLOCK1-10. 0x1C4 0x20 KEY5_ERR_NUM The value of this signal means the number of error bytes. 0 3 read-only KEY5_FAIL 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 3 1 read-only SYS_PART2_ERR_NUM The value of this signal means the number of error bytes. 4 3 read-only SYS_PART2_FAIL 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 7 1 read-only CLK eFuse clcok configuration register. 0x1C8 0x20 0x00000002 EFUSE_MEM_FORCE_PD Set this bit to force eFuse SRAM into power-saving mode. 0 1 read-write MEM_CLK_FORCE_ON Set this bit and force to activate clock signal of eFuse SRAM. 1 1 read-write EFUSE_MEM_FORCE_PU Set this bit to force eFuse SRAM into working mode. 2 1 read-write EN Set this bit and force to enable clock signal of eFuse memory. 16 1 read-write CONF eFuse operation mode configuraiton register; 0x1CC 0x20 OP_CODE 0x5A5A: Operate programming command 0x5AA5: Operate read command. 0 16 read-write STATUS eFuse status register. 0x1D0 0x20 STATE Indicates the state of the eFuse state machine. 0 4 read-only OTP_LOAD_SW The value of OTP_LOAD_SW. 4 1 read-only OTP_VDDQ_C_SYNC2 The value of OTP_VDDQ_C_SYNC2. 5 1 read-only OTP_STROBE_SW The value of OTP_STROBE_SW. 6 1 read-only OTP_CSB_SW The value of OTP_CSB_SW. 7 1 read-only OTP_PGENB_SW The value of OTP_PGENB_SW. 8 1 read-only OTP_VDDQ_IS_SW The value of OTP_VDDQ_IS_SW. 9 1 read-only REPEAT_ERR_CNT Indicates the number of error bits during programming BLOCK0. 10 8 read-only CMD eFuse command register. 0x1D4 0x20 READ_CMD Set this bit to send read command. 0 1 read-write PGM_CMD Set this bit to send programming command. 1 1 read-write BLK_NUM The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. 2 4 read-write INT_RAW eFuse raw interrupt register. 0x1D8 0x20 READ_DONE_INT_RAW The raw bit signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. 1 1 read-write INT_ST eFuse interrupt status register. 0x1DC 0x20 READ_DONE_INT_ST The status signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_ST The status signal for pgm_done interrupt. 1 1 read-only INT_ENA eFuse interrupt enable register. 0x1E0 0x20 READ_DONE_INT_ENA The enable signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_ENA The enable signal for pgm_done interrupt. 1 1 read-write INT_CLR eFuse interrupt clear register. 0x1E4 0x20 READ_DONE_INT_CLR The clear signal for read_done interrupt. 0 1 write-only PGM_DONE_INT_CLR The clear signal for pgm_done interrupt. 1 1 write-only DAC_CONF Controls the eFuse programming voltage. 0x1E8 0x20 0x0001FE1C DAC_CLK_DIV Controls the division factor of the rising clock of the programming voltage. 0 8 read-write DAC_CLK_PAD_SEL Don't care. 8 1 read-write DAC_NUM Controls the rising period of the programming voltage. 9 8 read-write OE_CLR Reduces the power supply of the programming voltage. 17 1 read-write RD_TIM_CONF Configures read timing parameters. 0x1EC 0x20 0x12000000 READ_INIT_NUM Configures the initial read time of eFuse. 24 8 read-write WR_TIM_CONF1 Configurarion register 1 of eFuse programming timing parameters. 0x1F0 0x20 0x00288000 PWR_ON_NUM Configures the power up time for VDDQ. 8 16 read-write WR_TIM_CONF2 Configurarion register 2 of eFuse programming timing parameters. 0x1F4 0x20 0x00000190 PWR_OFF_NUM Configures the power outage time for VDDQ. 0 16 read-write DATE eFuse version register. 0x1FC 0x20 0x02007200 DATE Stores eFuse version. 0 28 read-write EXTMEM External Memory EXTMEM 0x600C4000 0x0 0x108 registers ICACHE_CTRL This description will be updated in the near future. 0x0 0x20 ICACHE_ENABLE The bit is used to activate the data cache. 0: disable, 1: enable 0 1 read-write ICACHE_CTRL1 This description will be updated in the near future. 0x4 0x20 0x00000003 ICACHE_SHUT_IBUS The bit is used to disable core0 ibus, 0: enable, 1: disable 0 1 read-write ICACHE_SHUT_DBUS The bit is used to disable core1 ibus, 0: enable, 1: disable 1 1 read-write ICACHE_TAG_POWER_CTRL This description will be updated in the near future. 0x8 0x20 0x00000005 ICACHE_TAG_MEM_FORCE_ON The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. 0 1 read-write ICACHE_TAG_MEM_FORCE_PD The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down 1 1 read-write ICACHE_TAG_MEM_FORCE_PU The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up 2 1 read-write ICACHE_PRELOCK_CTRL This description will be updated in the near future. 0xC 0x20 ICACHE_PRELOCK_SCT0_EN The bit is used to enable the first section of prelock function. 0 1 read-write ICACHE_PRELOCK_SCT1_EN The bit is used to enable the second section of prelock function. 1 1 read-write ICACHE_PRELOCK_SCT0_ADDR This description will be updated in the near future. 0x10 0x20 ICACHE_PRELOCK_SCT0_ADDR The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG 0 32 read-write ICACHE_PRELOCK_SCT1_ADDR This description will be updated in the near future. 0x14 0x20 ICACHE_PRELOCK_SCT1_ADDR The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG 0 32 read-write ICACHE_PRELOCK_SCT_SIZE This description will be updated in the near future. 0x18 0x20 ICACHE_PRELOCK_SCT1_SIZE The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG 0 16 read-write ICACHE_PRELOCK_SCT0_SIZE The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG 16 16 read-write ICACHE_LOCK_CTRL This description will be updated in the near future. 0x1C 0x20 0x00000004 ICACHE_LOCK_ENA The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. 0 1 read-write ICACHE_UNLOCK_ENA The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. 1 1 read-write ICACHE_LOCK_DONE The bit is used to indicate unlock/lock operation is finished. 2 1 read-only ICACHE_LOCK_ADDR This description will be updated in the near future. 0x20 0x20 ICACHE_LOCK_ADDR The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. 0 32 read-write ICACHE_LOCK_SIZE This description will be updated in the near future. 0x24 0x20 ICACHE_LOCK_SIZE The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. 0 16 read-write ICACHE_SYNC_CTRL This description will be updated in the near future. 0x28 0x20 0x00000001 ICACHE_INVALIDATE_ENA The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. 0 1 read-write ICACHE_SYNC_DONE The bit is used to indicate invalidate operation is finished. 1 1 read-only ICACHE_SYNC_ADDR This description will be updated in the near future. 0x2C 0x20 ICACHE_SYNC_ADDR The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. 0 32 read-write ICACHE_SYNC_SIZE This description will be updated in the near future. 0x30 0x20 ICACHE_SYNC_SIZE The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. 0 23 read-write ICACHE_PRELOAD_CTRL This description will be updated in the near future. 0x34 0x20 0x00000002 ICACHE_PRELOAD_ENA The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. 0 1 read-write ICACHE_PRELOAD_DONE The bit is used to indicate preload operation is finished. 1 1 read-only ICACHE_PRELOAD_ORDER The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. 2 1 read-write ICACHE_PRELOAD_ADDR This description will be updated in the near future. 0x38 0x20 ICACHE_PRELOAD_ADDR The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. 0 32 read-write ICACHE_PRELOAD_SIZE This description will be updated in the near future. 0x3C 0x20 ICACHE_PRELOAD_SIZE The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. 0 16 read-write ICACHE_AUTOLOAD_CTRL This description will be updated in the near future. 0x40 0x20 0x00000008 ICACHE_AUTOLOAD_SCT0_ENA The bits are used to enable the first section for autoload operation. 0 1 read-write ICACHE_AUTOLOAD_SCT1_ENA The bits are used to enable the second section for autoload operation. 1 1 read-write ICACHE_AUTOLOAD_ENA The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. 2 1 read-write ICACHE_AUTOLOAD_DONE The bit is used to indicate autoload operation is finished. 3 1 read-only ICACHE_AUTOLOAD_ORDER The bits are used to configure the direction of autoload. 1: descending, 0: ascending. 4 1 read-write ICACHE_AUTOLOAD_RQST The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. 5 2 read-write ICACHE_AUTOLOAD_SCT0_ADDR This description will be updated in the near future. 0x44 0x20 ICACHE_AUTOLOAD_SCT0_ADDR The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. 0 32 read-write ICACHE_AUTOLOAD_SCT0_SIZE This description will be updated in the near future. 0x48 0x20 ICACHE_AUTOLOAD_SCT0_SIZE The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. 0 27 read-write ICACHE_AUTOLOAD_SCT1_ADDR This description will be updated in the near future. 0x4C 0x20 ICACHE_AUTOLOAD_SCT1_ADDR The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. 0 32 read-write ICACHE_AUTOLOAD_SCT1_SIZE This description will be updated in the near future. 0x50 0x20 ICACHE_AUTOLOAD_SCT1_SIZE The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. 0 27 read-write IBUS_TO_FLASH_START_VADDR This description will be updated in the near future. 0x54 0x20 0x42000000 IBUS_TO_FLASH_START_VADDR The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. 0 32 read-write IBUS_TO_FLASH_END_VADDR This description will be updated in the near future. 0x58 0x20 0x427FFFFF IBUS_TO_FLASH_END_VADDR The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. 0 32 read-write DBUS_TO_FLASH_START_VADDR This description will be updated in the near future. 0x5C 0x20 0x3C000000 DBUS_TO_FLASH_START_VADDR The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. 0 32 read-write DBUS_TO_FLASH_END_VADDR This description will be updated in the near future. 0x60 0x20 0x3C7FFFFF DBUS_TO_FLASH_END_VADDR The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. 0 32 read-write CACHE_ACS_CNT_CLR This description will be updated in the near future. 0x64 0x20 IBUS_ACS_CNT_CLR The bit is used to clear ibus counter. 0 1 write-only DBUS_ACS_CNT_CLR The bit is used to clear dbus counter. 1 1 write-only IBUS_ACS_MISS_CNT This description will be updated in the near future. 0x68 0x20 IBUS_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by ibus access flash. 0 32 read-only IBUS_ACS_CNT This description will be updated in the near future. 0x6C 0x20 IBUS_ACS_CNT The bits are used to count the number of ibus access flash through icache. 0 32 read-only DBUS_ACS_FLASH_MISS_CNT This description will be updated in the near future. 0x70 0x20 DBUS_ACS_FLASH_MISS_CNT The bits are used to count the number of the cache miss caused by dbus access flash. 0 32 read-only DBUS_ACS_CNT This description will be updated in the near future. 0x74 0x20 DBUS_ACS_CNT The bits are used to count the number of dbus access flash through icache. 0 32 read-only CACHE_ILG_INT_ENA This description will be updated in the near future. 0x78 0x20 ICACHE_SYNC_OP_FAULT_INT_ENA The bit is used to enable interrupt by sync configurations fault. 0 1 read-write ICACHE_PRELOAD_OP_FAULT_INT_ENA The bit is used to enable interrupt by preload configurations fault. 1 1 read-write MMU_ENTRY_FAULT_INT_ENA The bit is used to enable interrupt by mmu entry fault. 5 1 read-write IBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by ibus counter overflow. 7 1 read-write DBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by dbus counter overflow. 8 1 read-write CACHE_ILG_INT_CLR This description will be updated in the near future. 0x7C 0x20 ICACHE_SYNC_OP_FAULT_INT_CLR The bit is used to clear interrupt by sync configurations fault. 0 1 write-only ICACHE_PRELOAD_OP_FAULT_INT_CLR The bit is used to clear interrupt by preload configurations fault. 1 1 write-only MMU_ENTRY_FAULT_INT_CLR The bit is used to clear interrupt by mmu entry fault. 5 1 write-only IBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by ibus counter overflow. 7 1 write-only DBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by dbus counter overflow. 8 1 write-only CACHE_ILG_INT_ST This description will be updated in the near future. 0x80 0x20 ICACHE_SYNC_OP_FAULT_ST The bit is used to indicate interrupt by sync configurations fault. 0 1 read-only ICACHE_PRELOAD_OP_FAULT_ST The bit is used to indicate interrupt by preload configurations fault. 1 1 read-only MMU_ENTRY_FAULT_ST The bit is used to indicate interrupt by mmu entry fault. 5 1 read-only IBUS_ACS_CNT_OVF_ST The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. 7 1 read-only IBUS_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. 8 1 read-only DBUS_ACS_CNT_OVF_ST The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. 9 1 read-only DBUS_ACS_FLASH_MISS_CNT_OVF_ST The bit is used to indicate interrupt by dbus access flash miss counter overflow. 10 1 read-only CORE0_ACS_CACHE_INT_ENA This description will be updated in the near future. 0x84 0x20 CORE0_IBUS_ACS_MSK_IC_INT_ENA The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. 0 1 read-write CORE0_IBUS_WR_IC_INT_ENA The bit is used to enable interrupt by ibus trying to write icache 1 1 read-write CORE0_IBUS_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 2 1 read-write CORE0_DBUS_ACS_MSK_IC_INT_ENA The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. 3 1 read-write CORE0_DBUS_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 4 1 read-write CORE0_DBUS_WR_IC_INT_ENA The bit is used to enable interrupt by dbus trying to write icache 5 1 read-write CORE0_ACS_CACHE_INT_CLR This description will be updated in the near future. 0x88 0x20 CORE0_IBUS_ACS_MSK_IC_INT_CLR The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. 0 1 write-only CORE0_IBUS_WR_IC_INT_CLR The bit is used to clear interrupt by ibus trying to write icache 1 1 write-only CORE0_IBUS_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 2 1 write-only CORE0_DBUS_ACS_MSK_IC_INT_CLR The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. 3 1 write-only CORE0_DBUS_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 4 1 write-only CORE0_DBUS_WR_IC_INT_CLR The bit is used to clear interrupt by dbus trying to write icache 5 1 write-only CORE0_ACS_CACHE_INT_ST This description will be updated in the near future. 0x8C 0x20 CORE0_IBUS_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. 0 1 read-only CORE0_IBUS_WR_ICACHE_ST The bit is used to indicate interrupt by ibus trying to write icache 1 1 read-only CORE0_IBUS_REJECT_ST The bit is used to indicate interrupt by authentication fail. 2 1 read-only CORE0_DBUS_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. 3 1 read-only CORE0_DBUS_REJECT_ST The bit is used to indicate interrupt by authentication fail. 4 1 read-only CORE0_DBUS_WR_ICACHE_ST The bit is used to indicate interrupt by dbus trying to write icache 5 1 read-only CORE0_DBUS_REJECT_ST This description will be updated in the near future. 0x90 0x20 CORE0_DBUS_ATTR The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 0 3 read-only CORE0_DBUS_WORLD The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 3 1 read-only CORE0_DBUS_REJECT_VADDR This description will be updated in the near future. 0x94 0x20 0xFFFFFFFF CORE0_DBUS_VADDR The bits are used to indicate the virtual address of CPU access dbus when authentication fail. 0 32 read-only CORE0_IBUS_REJECT_ST This description will be updated in the near future. 0x98 0x20 CORE0_IBUS_ATTR The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able 0 3 read-only CORE0_IBUS_WORLD The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 3 1 read-only CORE0_IBUS_REJECT_VADDR This description will be updated in the near future. 0x9C 0x20 0xFFFFFFFF CORE0_IBUS_VADDR The bits are used to indicate the virtual address of CPU access ibus when authentication fail. 0 32 read-only CACHE_MMU_FAULT_CONTENT This description will be updated in the near future. 0xA0 0x20 CACHE_MMU_FAULT_CONTENT The bits are used to indicate the content of mmu entry which cause mmu fault.. 0 10 read-only CACHE_MMU_FAULT_CODE The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. 10 4 read-only CACHE_MMU_FAULT_VADDR This description will be updated in the near future. 0xA4 0x20 CACHE_MMU_FAULT_VADDR The bits are used to indicate the virtual address which cause mmu fault.. 0 32 read-only CACHE_WRAP_AROUND_CTRL This description will be updated in the near future. 0xA8 0x20 CACHE_FLASH_WRAP_AROUND The bit is used to enable wrap around mode when read data from flash. 0 1 read-write CACHE_MMU_POWER_CTRL This description will be updated in the near future. 0xAC 0x20 0x00000005 CACHE_MMU_MEM_FORCE_ON The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable 0 1 read-write CACHE_MMU_MEM_FORCE_PD The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down 1 1 read-write CACHE_MMU_MEM_FORCE_PU The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up 2 1 read-write CACHE_STATE This description will be updated in the near future. 0xB0 0x20 0x00000001 ICACHE_STATE The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state 0 12 read-only CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE This description will be updated in the near future. 0xB4 0x20 RECORD_DISABLE_DB_ENCRYPT Reserved. 0 1 read-write RECORD_DISABLE_G0CB_DECRYPT Reserved. 1 1 read-write CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON This description will be updated in the near future. 0xB8 0x20 0x00000007 CLK_FORCE_ON_MANUAL_CRYPT The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. 0 1 read-write CLK_FORCE_ON_AUTO_CRYPT The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. 1 1 read-write CLK_FORCE_ON_CRYPT The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. 2 1 read-write CACHE_PRELOAD_INT_CTRL This description will be updated in the near future. 0xBC 0x20 ICACHE_PRELOAD_INT_ST The bit is used to indicate the interrupt by icache pre-load done. 0 1 read-only ICACHE_PRELOAD_INT_ENA The bit is used to enable the interrupt by icache pre-load done. 1 1 read-write ICACHE_PRELOAD_INT_CLR The bit is used to clear the interrupt by icache pre-load done. 2 1 write-only CACHE_SYNC_INT_CTRL This description will be updated in the near future. 0xC0 0x20 ICACHE_SYNC_INT_ST The bit is used to indicate the interrupt by icache sync done. 0 1 read-only ICACHE_SYNC_INT_ENA The bit is used to enable the interrupt by icache sync done. 1 1 read-write ICACHE_SYNC_INT_CLR The bit is used to clear the interrupt by icache sync done. 2 1 write-only CACHE_MMU_OWNER This description will be updated in the near future. 0xC4 0x20 CACHE_MMU_OWNER The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus 0 4 read-write CACHE_CONF_MISC This description will be updated in the near future. 0xC8 0x20 0x00000007 CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by preload operation. 0 1 read-write CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by sync operation. 1 1 read-write CACHE_TRACE_ENA The bit is used to enable cache trace function. 2 1 read-write ICACHE_FREEZE This description will be updated in the near future. 0xCC 0x20 ENA The bit is used to enable icache freeze mode 0 1 read-write MODE The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss 1 1 read-write DONE The bit is used to indicate icache freeze success 2 1 read-only ICACHE_ATOMIC_OPERATE_ENA This description will be updated in the near future. 0xD0 0x20 0x00000001 ICACHE_ATOMIC_OPERATE_ENA The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. 0 1 read-write CACHE_REQUEST This description will be updated in the near future. 0xD4 0x20 BYPASS The bit is used to disable request recording which could cause performance issue 0 1 read-write IBUS_PMS_TBL_LOCK This description will be updated in the near future. 0xD8 0x20 IBUS_PMS_LOCK The bit is used to configure the ibus permission control section boundary0 0 1 read-write IBUS_PMS_TBL_BOUNDARY0 This description will be updated in the near future. 0xDC 0x20 IBUS_PMS_BOUNDARY0 The bit is used to configure the ibus permission control section boundary0 0 12 read-write IBUS_PMS_TBL_BOUNDARY1 This description will be updated in the near future. 0xE0 0x20 0x00000800 IBUS_PMS_BOUNDARY1 The bit is used to configure the ibus permission control section boundary1 0 12 read-write IBUS_PMS_TBL_BOUNDARY2 This description will be updated in the near future. 0xE4 0x20 0x00000800 IBUS_PMS_BOUNDARY2 The bit is used to configure the ibus permission control section boundary2 0 12 read-write IBUS_PMS_TBL_ATTR This description will be updated in the near future. 0xE8 0x20 0x000000FF IBUS_PMS_SCT1_ATTR The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1 0 4 read-write IBUS_PMS_SCT2_ATTR The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1 4 4 read-write DBUS_PMS_TBL_LOCK This description will be updated in the near future. 0xEC 0x20 DBUS_PMS_LOCK The bit is used to configure the ibus permission control section boundary0 0 1 read-write DBUS_PMS_TBL_BOUNDARY0 This description will be updated in the near future. 0xF0 0x20 DBUS_PMS_BOUNDARY0 The bit is used to configure the dbus permission control section boundary0 0 12 read-write DBUS_PMS_TBL_BOUNDARY1 This description will be updated in the near future. 0xF4 0x20 0x00000800 DBUS_PMS_BOUNDARY1 The bit is used to configure the dbus permission control section boundary1 0 12 read-write DBUS_PMS_TBL_BOUNDARY2 This description will be updated in the near future. 0xF8 0x20 0x00000800 DBUS_PMS_BOUNDARY2 The bit is used to configure the dbus permission control section boundary2 0 12 read-write DBUS_PMS_TBL_ATTR This description will be updated in the near future. 0xFC 0x20 0x0000000F DBUS_PMS_SCT1_ATTR The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1 0 2 read-write DBUS_PMS_SCT2_ATTR The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1 2 2 read-write CLOCK_GATE This description will be updated in the near future. 0x100 0x20 0x00000001 CLK_EN clock gate enable. 0 1 read-write REG_DATE This description will be updated in the near future. 0x3FC 0x20 0x02007160 DATE version information 0 28 read-write GPIO General Purpose Input/Output GPIO 0x60004000 0x0 0x31C registers GPIO 16 GPIO_NMI 17 BT_SELECT GPIO bit select register 0x0 0x20 BT_SEL GPIO bit select register 0 32 read-write OUT GPIO output register 0x4 0x20 DATA_ORIG GPIO output register for GPIO0-25 0 26 read-write OUT_W1TS GPIO output set register 0x8 0x20 OUT_W1TS GPIO output set register for GPIO0-25 0 26 write-only OUT_W1TC GPIO output clear register 0xC 0x20 OUT_W1TC GPIO output clear register for GPIO0-25 0 26 write-only SDIO_SELECT GPIO sdio select register 0x1C 0x20 SDIO_SEL GPIO sdio select register 0 8 read-write ENABLE GPIO output enable register 0x20 0x20 DATA GPIO output enable register for GPIO0-25 0 26 read-write ENABLE_W1TS GPIO output enable set register 0x24 0x20 ENABLE_W1TS GPIO output enable set register for GPIO0-25 0 26 write-only ENABLE_W1TC GPIO output enable clear register 0x28 0x20 ENABLE_W1TC GPIO output enable clear register for GPIO0-25 0 26 write-only STRAP pad strapping register 0x38 0x20 STRAPPING pad strapping register 0 16 read-only IN GPIO input register 0x3C 0x20 DATA_NEXT GPIO input register for GPIO0-25 0 26 read-only STATUS GPIO interrupt status register 0x44 0x20 INTERRUPT GPIO interrupt status register for GPIO0-25 0 26 read-write STATUS_W1TS GPIO interrupt status set register 0x48 0x20 STATUS_W1TS GPIO interrupt status set register for GPIO0-25 0 26 write-only STATUS_W1TC GPIO interrupt status clear register 0x4C 0x20 STATUS_W1TC GPIO interrupt status clear register for GPIO0-25 0 26 write-only PCPU_INT GPIO PRO_CPU interrupt status register 0x5C 0x20 PROCPU_INT GPIO PRO_CPU interrupt status register for GPIO0-25 0 26 read-only PCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register 0x60 0x20 PROCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25 0 26 read-only CPUSDIO_INT GPIO CPUSDIO interrupt status register 0x64 0x20 SDIO_INT GPIO CPUSDIO interrupt status register for GPIO0-25 0 26 read-only 26 0x4 0-25 PIN%s GPIO pin configuration register 0x74 0x20 SYNC2_BYPASS set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write PAD_DRIVER set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write SYNC1_BYPASS set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write INT_TYPE set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write CONFIG reserved 11 2 read-write INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 read-write STATUS_NEXT GPIO interrupt source register 0x14C 0x20 STATUS_INTERRUPT_NEXT GPIO interrupt source register for GPIO0-25 0 26 read-only 128 0x4 0-127 FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 0x20 IN_SEL set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 5 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 5 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 6 1 read-write 26 0x4 0-25 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 0x20 0x00000080 OUT_SEL The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write INV_SEL set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write OEN_SEL set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write OEN_INV_SEL set this bit to invert output enable signal.1:invert.0:not invert. 10 1 read-write CLOCK_GATE GPIO clock gate register 0x62C 0x20 0x00000001 CLK_EN set this bit to enable GPIO clock gate 0 1 read-write REG_DATE GPIO version register 0x6FC 0x20 0x02006130 REG_DATE version register 0 28 read-write GPIOSD Sigma-Delta Modulation GPIOSD 0x60004F00 0x0 0x1C registers 4 0x4 SIGMADELTA%s Duty Cycle Configure Register of SDM%s 0x0 0x20 0x0000FF00 SD0_IN This field is used to configure the duty cycle of sigma delta modulation output. 0 8 read-write SD0_PRESCALE This field is used to set a divider value to divide APB clock. 8 8 read-write SIGMADELTA_CG Clock Gating Configure Register 0x20 0x20 CLK_EN Clock enable bit of configuration registers for sigma delta modulation. 31 1 read-write SIGMADELTA_MISC MISC Register 0x24 0x20 FUNCTION_CLK_EN Clock enable bit of sigma delta modulation. 30 1 read-write SPI_SWAP Reserved. 31 1 read-write SIGMADELTA_VERSION Version Control Register 0x28 0x20 0x02006230 GPIO_SD_DATE Version control register. 0 28 read-write HMAC HMAC (Hash-based Message Authentication Code) Accelerator HMAC 0x6003E000 0x0 0xA4 registers SET_START Process control register 0. 0x40 0x20 SET_START Start hmac operation. 0 1 write-only SET_PARA_PURPOSE Configure purpose. 0x44 0x20 PURPOSE_SET Set hmac parameter purpose. 0 4 write-only SET_PARA_KEY Configure key. 0x48 0x20 KEY_SET Set hmac parameter key. 0 3 write-only SET_PARA_FINISH Finish initial configuration. 0x4C 0x20 SET_PARA_END Finish hmac configuration. 0 1 write-only SET_MESSAGE_ONE Process control register 1. 0x50 0x20 SET_TEXT_ONE Call SHA to calculate one message block. 0 1 write-only SET_MESSAGE_ING Process control register 2. 0x54 0x20 SET_TEXT_ING Continue typical hmac. 0 1 write-only SET_MESSAGE_END Process control register 3. 0x58 0x20 SET_TEXT_END Start hardware padding. 0 1 write-only SET_RESULT_FINISH Process control register 4. 0x5C 0x20 SET_RESULT_END After read result from upstream, then let hmac back to idle. 0 1 write-only SET_INVALIDATE_JTAG Invalidate register 0. 0x60 0x20 SET_INVALIDATE_JTAG Clear result from hmac downstream JTAG. 0 1 write-only SET_INVALIDATE_DS Invalidate register 1. 0x64 0x20 SET_INVALIDATE_DS Clear result from hmac downstream DS. 0 1 write-only QUERY_ERROR Error register. 0x68 0x20 QUREY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 read-only QUERY_BUSY Busy register. 0x6C 0x20 BUSY_STATE Hmac state. 1'b0: idle. 1'b1: busy 0 1 read-only 64 0x1 WR_MESSAGE_MEM[%s] Message block memory. 0x80 0x8 32 0x1 RD_RESULT_MEM[%s] Result from upstream. 0xC0 0x8 SET_MESSAGE_PAD Process control register 5. 0xF0 0x20 SET_TEXT_PAD Start software padding. 0 1 write-only ONE_BLOCK Process control register 6. 0xF4 0x20 SET_ONE_BLOCK Don't have to do padding. 0 1 write-only SOFT_JTAG_CTRL Jtag register 0. 0xF8 0x20 SOFT_JTAG_CTRL Turn on JTAG verification. 0 1 write-only WR_JTAG Jtag register 1. 0xFC 0x20 WR_JTAG 32-bit of key to be compared. 0 32 write-only I2C0 I2C (Inter-Integrated Circuit) Controller I2C 0x60013000 0x0 0x90 registers I2C_EXT0 29 SCL_LOW_PERIOD I2C_SCL_LOW_PERIOD_REG 0x0 0x20 SCL_LOW_PERIOD reg_scl_low_period 0 9 read-write CTR I2C_CTR_REG 0x4 0x20 0x0000020B SDA_FORCE_OUT reg_sda_force_out 0 1 read-write SCL_FORCE_OUT reg_scl_force_out 1 1 read-write SAMPLE_SCL_LEVEL reg_sample_scl_level 2 1 read-write RX_FULL_ACK_LEVEL reg_rx_full_ack_level 3 1 read-write MS_MODE reg_ms_mode 4 1 read-write TRANS_START reg_trans_start 5 1 write-only TX_LSB_FIRST reg_tx_lsb_first 6 1 read-write RX_LSB_FIRST reg_rx_lsb_first 7 1 read-write CLK_EN reg_clk_en 8 1 read-write ARBITRATION_EN reg_arbitration_en 9 1 read-write FSM_RST reg_fsm_rst 10 1 write-only CONF_UPGATE reg_conf_upgate 11 1 write-only SLV_TX_AUTO_START_EN reg_slv_tx_auto_start_en 12 1 read-write ADDR_10BIT_RW_CHECK_EN reg_addr_10bit_rw_check_en 13 1 read-write ADDR_BROADCASTING_EN reg_addr_broadcasting_en 14 1 read-write SR I2C_SR_REG 0x8 0x20 0x0000C000 RESP_REC reg_resp_rec 0 1 read-only SLAVE_RW reg_slave_rw 1 1 read-only ARB_LOST reg_arb_lost 3 1 read-only BUS_BUSY reg_bus_busy 4 1 read-only SLAVE_ADDRESSED reg_slave_addressed 5 1 read-only RXFIFO_CNT reg_rxfifo_cnt 8 6 read-only STRETCH_CAUSE reg_stretch_cause 14 2 read-only TXFIFO_CNT reg_txfifo_cnt 18 6 read-only SCL_MAIN_STATE_LAST reg_scl_main_state_last 24 3 read-only SCL_STATE_LAST reg_scl_state_last 28 3 read-only TO I2C_TO_REG 0xC 0x20 0x00000010 TIME_OUT_VALUE reg_time_out_value 0 5 read-write TIME_OUT_EN reg_time_out_en 5 1 read-write SLAVE_ADDR I2C_SLAVE_ADDR_REG 0x10 0x20 SLAVE_ADDR reg_slave_addr 0 15 read-write ADDR_10BIT_EN reg_addr_10bit_en 31 1 read-write FIFO_ST I2C_FIFO_ST_REG 0x14 0x20 RXFIFO_RADDR reg_rxfifo_raddr 0 5 read-only RXFIFO_WADDR reg_rxfifo_waddr 5 5 read-only TXFIFO_RADDR reg_txfifo_raddr 10 5 read-only TXFIFO_WADDR reg_txfifo_waddr 15 5 read-only SLAVE_RW_POINT reg_slave_rw_point 22 8 read-only FIFO_CONF I2C_FIFO_CONF_REG 0x18 0x20 0x0000408B RXFIFO_WM_THRHD reg_rxfifo_wm_thrhd 0 5 read-write TXFIFO_WM_THRHD reg_txfifo_wm_thrhd 5 5 read-write NONFIFO_EN reg_nonfifo_en 10 1 read-write FIFO_ADDR_CFG_EN reg_fifo_addr_cfg_en 11 1 read-write RX_FIFO_RST reg_rx_fifo_rst 12 1 read-write TX_FIFO_RST reg_tx_fifo_rst 13 1 read-write FIFO_PRT_EN reg_fifo_prt_en 14 1 read-write DATA I2C_FIFO_DATA_REG 0x1C 0x20 FIFO_RDATA reg_fifo_rdata 0 8 read-write INT_RAW I2C_INT_RAW_REG 0x20 0x20 0x00000002 RXFIFO_WM_INT_RAW reg_rxfifo_wm_int_raw 0 1 read-only TXFIFO_WM_INT_RAW reg_txfifo_wm_int_raw 1 1 read-only RXFIFO_OVF_INT_RAW reg_rxfifo_ovf_int_raw 2 1 read-only END_DETECT_INT_RAW reg_end_detect_int_raw 3 1 read-only BYTE_TRANS_DONE_INT_RAW reg_byte_trans_done_int_raw 4 1 read-only ARBITRATION_LOST_INT_RAW reg_arbitration_lost_int_raw 5 1 read-only MST_TXFIFO_UDF_INT_RAW reg_mst_txfifo_udf_int_raw 6 1 read-only TRANS_COMPLETE_INT_RAW reg_trans_complete_int_raw 7 1 read-only TIME_OUT_INT_RAW reg_time_out_int_raw 8 1 read-only TRANS_START_INT_RAW reg_trans_start_int_raw 9 1 read-only NACK_INT_RAW reg_nack_int_raw 10 1 read-only TXFIFO_OVF_INT_RAW reg_txfifo_ovf_int_raw 11 1 read-only RXFIFO_UDF_INT_RAW reg_rxfifo_udf_int_raw 12 1 read-only SCL_ST_TO_INT_RAW reg_scl_st_to_int_raw 13 1 read-only SCL_MAIN_ST_TO_INT_RAW reg_scl_main_st_to_int_raw 14 1 read-only DET_START_INT_RAW reg_det_start_int_raw 15 1 read-only SLAVE_STRETCH_INT_RAW reg_slave_stretch_int_raw 16 1 read-only GENERAL_CALL_INT_RAW reg_general_call_int_raw 17 1 read-only INT_CLR I2C_INT_CLR_REG 0x24 0x20 RXFIFO_WM_INT_CLR reg_rxfifo_wm_int_clr 0 1 write-only TXFIFO_WM_INT_CLR reg_txfifo_wm_int_clr 1 1 write-only RXFIFO_OVF_INT_CLR reg_rxfifo_ovf_int_clr 2 1 write-only END_DETECT_INT_CLR reg_end_detect_int_clr 3 1 write-only BYTE_TRANS_DONE_INT_CLR reg_byte_trans_done_int_clr 4 1 write-only ARBITRATION_LOST_INT_CLR reg_arbitration_lost_int_clr 5 1 write-only MST_TXFIFO_UDF_INT_CLR reg_mst_txfifo_udf_int_clr 6 1 write-only TRANS_COMPLETE_INT_CLR reg_trans_complete_int_clr 7 1 write-only TIME_OUT_INT_CLR reg_time_out_int_clr 8 1 write-only TRANS_START_INT_CLR reg_trans_start_int_clr 9 1 write-only NACK_INT_CLR reg_nack_int_clr 10 1 write-only TXFIFO_OVF_INT_CLR reg_txfifo_ovf_int_clr 11 1 write-only RXFIFO_UDF_INT_CLR reg_rxfifo_udf_int_clr 12 1 write-only SCL_ST_TO_INT_CLR reg_scl_st_to_int_clr 13 1 write-only SCL_MAIN_ST_TO_INT_CLR reg_scl_main_st_to_int_clr 14 1 write-only DET_START_INT_CLR reg_det_start_int_clr 15 1 write-only SLAVE_STRETCH_INT_CLR reg_slave_stretch_int_clr 16 1 write-only GENERAL_CALL_INT_CLR reg_general_call_int_clr 17 1 write-only INT_ENA I2C_INT_ENA_REG 0x28 0x20 RXFIFO_WM_INT_ENA reg_rxfifo_wm_int_ena 0 1 read-write TXFIFO_WM_INT_ENA reg_txfifo_wm_int_ena 1 1 read-write RXFIFO_OVF_INT_ENA reg_rxfifo_ovf_int_ena 2 1 read-write END_DETECT_INT_ENA reg_end_detect_int_ena 3 1 read-write BYTE_TRANS_DONE_INT_ENA reg_byte_trans_done_int_ena 4 1 read-write ARBITRATION_LOST_INT_ENA reg_arbitration_lost_int_ena 5 1 read-write MST_TXFIFO_UDF_INT_ENA reg_mst_txfifo_udf_int_ena 6 1 read-write TRANS_COMPLETE_INT_ENA reg_trans_complete_int_ena 7 1 read-write TIME_OUT_INT_ENA reg_time_out_int_ena 8 1 read-write TRANS_START_INT_ENA reg_trans_start_int_ena 9 1 read-write NACK_INT_ENA reg_nack_int_ena 10 1 read-write TXFIFO_OVF_INT_ENA reg_txfifo_ovf_int_ena 11 1 read-write RXFIFO_UDF_INT_ENA reg_rxfifo_udf_int_ena 12 1 read-write SCL_ST_TO_INT_ENA reg_scl_st_to_int_ena 13 1 read-write SCL_MAIN_ST_TO_INT_ENA reg_scl_main_st_to_int_ena 14 1 read-write DET_START_INT_ENA reg_det_start_int_ena 15 1 read-write SLAVE_STRETCH_INT_ENA reg_slave_stretch_int_ena 16 1 read-write GENERAL_CALL_INT_ENA reg_general_call_int_ena 17 1 read-write INT_STATUS I2C_INT_STATUS_REG 0x2C 0x20 RXFIFO_WM_INT_ST reg_rxfifo_wm_int_st 0 1 read-only TXFIFO_WM_INT_ST reg_txfifo_wm_int_st 1 1 read-only RXFIFO_OVF_INT_ST reg_rxfifo_ovf_int_st 2 1 read-only END_DETECT_INT_ST reg_end_detect_int_st 3 1 read-only BYTE_TRANS_DONE_INT_ST reg_byte_trans_done_int_st 4 1 read-only ARBITRATION_LOST_INT_ST reg_arbitration_lost_int_st 5 1 read-only MST_TXFIFO_UDF_INT_ST reg_mst_txfifo_udf_int_st 6 1 read-only TRANS_COMPLETE_INT_ST reg_trans_complete_int_st 7 1 read-only TIME_OUT_INT_ST reg_time_out_int_st 8 1 read-only TRANS_START_INT_ST reg_trans_start_int_st 9 1 read-only NACK_INT_ST reg_nack_int_st 10 1 read-only TXFIFO_OVF_INT_ST reg_txfifo_ovf_int_st 11 1 read-only RXFIFO_UDF_INT_ST reg_rxfifo_udf_int_st 12 1 read-only SCL_ST_TO_INT_ST reg_scl_st_to_int_st 13 1 read-only SCL_MAIN_ST_TO_INT_ST reg_scl_main_st_to_int_st 14 1 read-only DET_START_INT_ST reg_det_start_int_st 15 1 read-only SLAVE_STRETCH_INT_ST reg_slave_stretch_int_st 16 1 read-only GENERAL_CALL_INT_ST reg_general_call_int_st 17 1 read-only SDA_HOLD I2C_SDA_HOLD_REG 0x30 0x20 TIME reg_sda_hold_time 0 9 read-write SDA_SAMPLE I2C_SDA_SAMPLE_REG 0x34 0x20 TIME reg_sda_sample_time 0 9 read-write SCL_HIGH_PERIOD I2C_SCL_HIGH_PERIOD_REG 0x38 0x20 SCL_HIGH_PERIOD reg_scl_high_period 0 9 read-write SCL_WAIT_HIGH_PERIOD reg_scl_wait_high_period 9 7 read-write SCL_START_HOLD I2C_SCL_START_HOLD_REG 0x40 0x20 0x00000008 TIME reg_scl_start_hold_time 0 9 read-write SCL_RSTART_SETUP I2C_SCL_RSTART_SETUP_REG 0x44 0x20 0x00000008 TIME reg_scl_rstart_setup_time 0 9 read-write SCL_STOP_HOLD I2C_SCL_STOP_HOLD_REG 0x48 0x20 0x00000008 TIME reg_scl_stop_hold_time 0 9 read-write SCL_STOP_SETUP I2C_SCL_STOP_SETUP_REG 0x4C 0x20 0x00000008 TIME reg_scl_stop_setup_time 0 9 read-write FILTER_CFG I2C_FILTER_CFG_REG 0x50 0x20 0x00000300 SCL_FILTER_THRES reg_scl_filter_thres 0 4 read-write SDA_FILTER_THRES reg_sda_filter_thres 4 4 read-write SCL_FILTER_EN reg_scl_filter_en 8 1 read-write SDA_FILTER_EN reg_sda_filter_en 9 1 read-write CLK_CONF I2C_CLK_CONF_REG 0x54 0x20 0x00200000 SCLK_DIV_NUM reg_sclk_div_num 0 8 read-write SCLK_DIV_A reg_sclk_div_a 8 6 read-write SCLK_DIV_B reg_sclk_div_b 14 6 read-write SCLK_SEL reg_sclk_sel 20 1 read-write SCLK_ACTIVE reg_sclk_active 21 1 read-write 8 0x4 0-7 COMD%s I2C_COMD%s_REG 0x58 0x20 COMMAND reg_command 0 14 read-write COMMAND_DONE reg_command_done 31 1 read-write SCL_ST_TIME_OUT I2C_SCL_ST_TIME_OUT_REG 0x78 0x20 0x00000010 SCL_ST_TO_I2C reg_scl_st_to_regno more than 23 0 5 read-write SCL_MAIN_ST_TIME_OUT I2C_SCL_MAIN_ST_TIME_OUT_REG 0x7C 0x20 0x00000010 SCL_MAIN_ST_TO_I2C reg_scl_main_st_to_regno more than 23 0 5 read-write SCL_SP_CONF I2C_SCL_SP_CONF_REG 0x80 0x20 SCL_RST_SLV_EN reg_scl_rst_slv_en 0 1 read-write SCL_RST_SLV_NUM reg_scl_rst_slv_num 1 5 read-write SCL_PD_EN reg_scl_pd_en 6 1 read-write SDA_PD_EN reg_sda_pd_en 7 1 read-write SCL_STRETCH_CONF I2C_SCL_STRETCH_CONF_REG 0x84 0x20 STRETCH_PROTECT_NUM reg_stretch_protect_num 0 10 read-write SLAVE_SCL_STRETCH_EN reg_slave_scl_stretch_en 10 1 read-write SLAVE_SCL_STRETCH_CLR reg_slave_scl_stretch_clr 11 1 write-only SLAVE_BYTE_ACK_CTL_EN reg_slave_byte_ack_ctl_en 12 1 read-write SLAVE_BYTE_ACK_LVL reg_slave_byte_ack_lvl 13 1 read-write DATE I2C_DATE_REG 0xF8 0x20 0x20070201 DATE reg_date 0 32 read-write TXFIFO_START_ADDR I2C_TXFIFO_START_ADDR_REG 0x100 0x20 TXFIFO_START_ADDR reg_txfifo_start_addr. 0 32 read-only RXFIFO_START_ADDR I2C_RXFIFO_START_ADDR_REG 0x180 0x20 RXFIFO_START_ADDR reg_rxfifo_start_addr. 0 32 read-only I2S I2S (Inter-IC Sound) Controller I2S 0x6002D000 0x0 0x5C registers I2S 20 INT_RAW I2S interrupt raw register, valid in level. 0xC 0x20 RX_DONE_INT_RAW The raw interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only TX_DONE_INT_RAW The raw interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only RX_HUNG_INT_RAW The raw interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only TX_HUNG_INT_RAW The raw interrupt status bit for the i2s_tx_hung_int interrupt 3 1 read-only INT_ST I2S interrupt status register. 0x10 0x20 RX_DONE_INT_ST The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only TX_DONE_INT_ST The masked interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only RX_HUNG_INT_ST The masked interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only TX_HUNG_INT_ST The masked interrupt status bit for the i2s_tx_hung_int interrupt 3 1 read-only INT_ENA I2S interrupt enable register. 0x14 0x20 RX_DONE_INT_ENA The interrupt enable bit for the i2s_rx_done_int interrupt 0 1 read-write TX_DONE_INT_ENA The interrupt enable bit for the i2s_tx_done_int interrupt 1 1 read-write RX_HUNG_INT_ENA The interrupt enable bit for the i2s_rx_hung_int interrupt 2 1 read-write TX_HUNG_INT_ENA The interrupt enable bit for the i2s_tx_hung_int interrupt 3 1 read-write INT_CLR I2S interrupt clear register. 0x18 0x20 RX_DONE_INT_CLR Set this bit to clear the i2s_rx_done_int interrupt 0 1 write-only TX_DONE_INT_CLR Set this bit to clear the i2s_tx_done_int interrupt 1 1 write-only RX_HUNG_INT_CLR Set this bit to clear the i2s_rx_hung_int interrupt 2 1 write-only TX_HUNG_INT_CLR Set this bit to clear the i2s_tx_hung_int interrupt 3 1 write-only RX_CONF I2S RX configure register 0x20 0x20 0x00009600 RX_RESET Set this bit to reset receiver 0 1 write-only RX_FIFO_RESET Set this bit to reset Rx AFIFO 1 1 write-only RX_START Set this bit to start receiving data 2 1 read-write RX_SLAVE_MOD Set this bit to enable slave receiver mode 3 1 read-write RX_MONO Set this bit to enable receiver in mono mode 5 1 read-write RX_BIG_ENDIAN I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write RX_UPDATE Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write RX_MONO_FST_VLD 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write RX_PCM_CONF I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write RX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for received data. 12 1 read-write RX_STOP_MODE 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 13 2 read-write RX_LEFT_ALIGN 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. 15 1 read-write RX_24_FILL_EN 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. 16 1 read-write RX_WS_IDLE_POL 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. 17 1 read-write RX_BIT_ORDER I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. 18 1 read-write RX_TDM_EN 1: Enable I2S TDM Rx mode . 0: Disable. 19 1 read-write RX_PDM_EN 1: Enable I2S PDM Rx mode . 0: Disable. 20 1 read-write TX_CONF I2S TX configure register 0x24 0x20 0x0000B200 TX_RESET Set this bit to reset transmitter 0 1 write-only TX_FIFO_RESET Set this bit to reset Tx AFIFO 1 1 write-only TX_START Set this bit to start transmitting data 2 1 read-write TX_SLAVE_MOD Set this bit to enable slave transmitter mode 3 1 read-write TX_MONO Set this bit to enable transmitter in mono mode 5 1 read-write TX_CHAN_EQUAL 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 6 1 read-write TX_BIG_ENDIAN I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write TX_UPDATE Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write TX_MONO_FST_VLD 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. 9 1 read-write TX_PCM_CONF I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write TX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for transmitted data. 12 1 read-write TX_STOP_EN Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 13 1 read-write TX_LEFT_ALIGN 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. 15 1 read-write TX_24_FILL_EN 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode 16 1 read-write TX_WS_IDLE_POL 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. 17 1 read-write TX_BIT_ORDER I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. 18 1 read-write TX_TDM_EN 1: Enable I2S TDM Tx mode . 0: Disable. 19 1 read-write TX_PDM_EN 1: Enable I2S PDM Tx mode . 0: Disable. 20 1 read-write TX_CHAN_MOD I2S transmitter channel mode configuration bits. 24 3 read-write SIG_LOOPBACK Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. 27 1 read-write RX_CONF1 I2S RX configure register 1 0x28 0x20 0x2F3DE300 RX_TDM_WS_WIDTH The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write RX_BCK_DIV_NUM Bit clock configuration bits in receiver mode. 7 6 read-write RX_BITS_MOD Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write RX_HALF_SAMPLE_BITS I2S Rx half sample bits -1. 18 6 read-write RX_TDM_CHAN_BITS The Rx bit number for each channel minus 1in TDM mode. 24 5 read-write RX_MSB_SHIFT Set this bit to enable receiver in Phillips standard mode 29 1 read-write TX_CONF1 I2S TX configure register 1 0x2C 0x20 0x6F3DE300 TX_TDM_WS_WIDTH The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write TX_BCK_DIV_NUM Bit clock configuration bits in transmitter mode. 7 6 read-write TX_BITS_MOD Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write TX_HALF_SAMPLE_BITS I2S Tx half sample bits -1. 18 6 read-write TX_TDM_CHAN_BITS The Tx bit number for each channel minus 1in TDM mode. 24 5 read-write TX_MSB_SHIFT Set this bit to enable transmitter in Phillips standard mode 29 1 read-write TX_BCK_NO_DLY 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. 30 1 read-write RX_CLKM_CONF I2S RX clock configure register 0x30 0x20 0x00000002 RX_CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write RX_CLK_ACTIVE I2S Rx module clock enable signal. 26 1 read-write RX_CLK_SEL Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write MCLK_SEL 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. 29 1 read-write TX_CLKM_CONF I2S TX clock configure register 0x34 0x20 0x00000002 TX_CLKM_DIV_NUM Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. 0 8 read-write TX_CLK_ACTIVE I2S Tx module clock enable signal. 26 1 read-write TX_CLK_SEL Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write CLK_EN Set this bit to enable clk gate 29 1 read-write RX_CLKM_DIV_CONF I2S RX module clock divider configure register 0x38 0x20 0x00000200 RX_CLKM_DIV_Z For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). 0 9 read-write RX_CLKM_DIV_Y For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write RX_CLKM_DIV_X For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write RX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. 27 1 read-write TX_CLKM_DIV_CONF I2S TX module clock divider configure register 0x3C 0x20 0x00000200 TX_CLKM_DIV_Z For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). 0 9 read-write TX_CLKM_DIV_Y For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write TX_CLKM_DIV_X For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write TX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. 27 1 read-write TX_PCM2PDM_CONF I2S TX PCM2PDM configuration register 0x40 0x20 0x004AA004 TX_PDM_HP_BYPASS I2S TX PDM bypass hp filter or not. The option has been removed. 0 1 read-write TX_PDM_SINC_OSR2 I2S TX PDM OSR2 value 1 4 read-write TX_PDM_PRESCALE I2S TX PDM prescale for sigmadelta 5 8 read-write TX_PDM_HP_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 13 2 read-write TX_PDM_LP_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 15 2 read-write TX_PDM_SINC_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 17 2 read-write TX_PDM_SIGMADELTA_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 19 2 read-write TX_PDM_SIGMADELTA_DITHER2 I2S TX PDM sigmadelta dither2 value 21 1 read-write TX_PDM_SIGMADELTA_DITHER I2S TX PDM sigmadelta dither value 22 1 read-write TX_PDM_DAC_2OUT_EN I2S TX PDM dac mode enable 23 1 read-write TX_PDM_DAC_MODE_EN I2S TX PDM dac 2channel enable 24 1 read-write PCM2PDM_CONV_EN I2S TX PDM Converter enable 25 1 read-write TX_PCM2PDM_CONF1 I2S TX PCM2PDM configuration register 0x44 0x20 0x03F783C0 TX_PDM_FP I2S TX PDM Fp 0 10 read-write TX_PDM_FS I2S TX PDM Fs 10 10 read-write TX_IIR_HP_MULT12_5 The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) 20 3 read-write TX_IIR_HP_MULT12_0 The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) 23 3 read-write RX_TDM_CTRL I2S TX TDM mode control register 0x50 0x20 0x0000FFFF RX_TDM_PDM_CHAN0_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 read-write RX_TDM_PDM_CHAN1_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 read-write RX_TDM_PDM_CHAN2_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 read-write RX_TDM_PDM_CHAN3_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 read-write RX_TDM_PDM_CHAN4_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 read-write RX_TDM_PDM_CHAN5_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 1 read-write RX_TDM_PDM_CHAN6_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. 6 1 read-write RX_TDM_PDM_CHAN7_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 read-write RX_TDM_CHAN8_EN 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 read-write RX_TDM_CHAN9_EN 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 read-write RX_TDM_CHAN10_EN 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 1 read-write RX_TDM_CHAN11_EN 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. 11 1 read-write RX_TDM_CHAN12_EN 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 1 read-write RX_TDM_CHAN13_EN 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. 13 1 read-write RX_TDM_CHAN14_EN 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. 14 1 read-write RX_TDM_CHAN15_EN 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 read-write RX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write TX_TDM_CTRL I2S TX TDM mode control register 0x54 0x20 0x0000FFFF TX_TDM_CHAN0_EN 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 read-write TX_TDM_CHAN1_EN 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 read-write TX_TDM_CHAN2_EN 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 read-write TX_TDM_CHAN3_EN 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 read-write TX_TDM_CHAN4_EN 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 read-write TX_TDM_CHAN5_EN 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 1 read-write TX_TDM_CHAN6_EN 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. 6 1 read-write TX_TDM_CHAN7_EN 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 read-write TX_TDM_CHAN8_EN 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 read-write TX_TDM_CHAN9_EN 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 read-write TX_TDM_CHAN10_EN 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 1 read-write TX_TDM_CHAN11_EN 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. 11 1 read-write TX_TDM_CHAN12_EN 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. 12 1 read-write TX_TDM_CHAN13_EN 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. 13 1 read-write TX_TDM_CHAN14_EN 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. 14 1 read-write TX_TDM_CHAN15_EN 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. 15 1 read-write TX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write TX_TDM_SKIP_MSK_EN When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. 20 1 read-write RX_TIMING I2S RX timing control register 0x58 0x20 RX_SD_IN_DM The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write RX_WS_OUT_DM The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write RX_BCK_OUT_DM The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write RX_WS_IN_DM The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write RX_BCK_IN_DM The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 read-write TX_TIMING I2S TX timing control register 0x5C 0x20 TX_SD_OUT_DM The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write TX_SD1_OUT_DM The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 2 read-write TX_WS_OUT_DM The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write TX_BCK_OUT_DM The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write TX_WS_IN_DM The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write TX_BCK_IN_DM The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 read-write LC_HUNG_CONF I2S HUNG configure register. 0x60 0x20 0x00000810 LC_FIFO_TIMEOUT the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value 0 8 read-write LC_FIFO_TIMEOUT_SHIFT The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift 8 3 read-write LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout 11 1 read-write RXEOF_NUM I2S RX data number control register. 0x64 0x20 0x00000040 RX_EOF_NUM The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 0 12 read-write CONF_SIGLE_DATA I2S signal data register 0x68 0x20 SINGLE_DATA The configured constant channel data to be sent out. 0 32 read-write STATE I2S TX status register 0x6C 0x20 0x00000001 TX_IDLE 1: i2s_tx is idle state. 0: i2s_tx is working. 0 1 read-only DATE Version control register 0x80 0x20 0x02007220 DATE I2S version control register 0 28 read-write INTERRUPT_CORE0 Interrupt Core INTERRUPT_CORE0 0x600C2000 0x0 0x19C registers WIFI_MAC 0 WIFI_MAC_NMI 1 WIFI_PWR 2 WIFI_BB 3 BT_MAC 4 BT_BB 5 BT_BB_NMI 6 RWBT 7 RWBLE 8 RWBT_NMI 9 RWBLE_NMI 10 SW_INTR_0 50 SW_INTR_1 51 SW_INTR_2 52 SW_INTR_3 53 MAC_INTR_MAP mac intr map register 0x0 0x20 MAC_INTR_MAP core0_mac_intr_map 0 5 read-write MAC_NMI_MAP mac nmi_intr map register 0x4 0x20 MAC_NMI_MAP reg_core0_mac_nmi_map 0 5 read-write PWR_INTR_MAP pwr intr map register 0x8 0x20 PWR_INTR_MAP reg_core0_pwr_intr_map 0 5 read-write BB_INT_MAP bb intr map register 0xC 0x20 BB_INT_MAP reg_core0_bb_int_map 0 5 read-write BT_MAC_INT_MAP bt intr map register 0x10 0x20 BT_MAC_INT_MAP reg_core0_bt_mac_int_map 0 5 read-write BT_BB_INT_MAP bb_bt intr map register 0x14 0x20 BT_BB_INT_MAP reg_core0_bt_bb_int_map 0 5 read-write BT_BB_NMI_MAP bb_bt_nmi intr map register 0x18 0x20 BT_BB_NMI_MAP reg_core0_bt_bb_nmi_map 0 5 read-write RWBT_IRQ_MAP rwbt intr map register 0x1C 0x20 RWBT_IRQ_MAP reg_core0_rwbt_irq_map 0 5 read-write RWBLE_IRQ_MAP rwble intr map register 0x20 0x20 RWBLE_IRQ_MAP reg_core0_rwble_irq_map 0 5 read-write RWBT_NMI_MAP rwbt_nmi intr map register 0x24 0x20 RWBT_NMI_MAP reg_core0_rwbt_nmi_map 0 5 read-write RWBLE_NMI_MAP rwble_nmi intr map register 0x28 0x20 RWBLE_NMI_MAP reg_core0_rwble_nmi_map 0 5 read-write I2C_MST_INT_MAP i2c intr map register 0x2C 0x20 I2C_MST_INT_MAP reg_core0_i2c_mst_int_map 0 5 read-write SLC0_INTR_MAP slc0 intr map register 0x30 0x20 SLC0_INTR_MAP reg_core0_slc0_intr_map 0 5 read-write SLC1_INTR_MAP slc1 intr map register 0x34 0x20 SLC1_INTR_MAP reg_core0_slc1_intr_map 0 5 read-write APB_CTRL_INTR_MAP apb_ctrl intr map register 0x38 0x20 APB_CTRL_INTR_MAP reg_core0_apb_ctrl_intr_map 0 5 read-write UHCI0_INTR_MAP uchi0 intr map register 0x3C 0x20 UHCI0_INTR_MAP reg_core0_uhci0_intr_map 0 5 read-write GPIO_INTERRUPT_PRO_MAP gpio intr map register 0x40 0x20 GPIO_INTERRUPT_PRO_MAP reg_core0_gpio_interrupt_pro_map 0 5 read-write GPIO_INTERRUPT_PRO_NMI_MAP gpio_pro intr map register 0x44 0x20 GPIO_INTERRUPT_PRO_NMI_MAP reg_core0_gpio_interrupt_pro_nmi_map 0 5 read-write SPI_INTR_1_MAP gpio_pro_nmi intr map register 0x48 0x20 SPI_INTR_1_MAP reg_core0_spi_intr_1_map 0 5 read-write SPI_INTR_2_MAP spi1 intr map register 0x4C 0x20 SPI_INTR_2_MAP reg_core0_spi_intr_2_map 0 5 read-write I2S1_INT_MAP spi2 intr map register 0x50 0x20 I2S1_INT_MAP reg_core0_i2s1_int_map 0 5 read-write UART_INTR_MAP i2s1 intr map register 0x54 0x20 UART_INTR_MAP reg_core0_uart_intr_map 0 5 read-write UART1_INTR_MAP uart1 intr map register 0x58 0x20 UART1_INTR_MAP reg_core0_uart1_intr_map 0 5 read-write LEDC_INT_MAP ledc intr map register 0x5C 0x20 LEDC_INT_MAP reg_core0_ledc_int_map 0 5 read-write EFUSE_INT_MAP efuse intr map register 0x60 0x20 EFUSE_INT_MAP reg_core0_efuse_int_map 0 5 read-write CAN_INT_MAP can intr map register 0x64 0x20 CAN_INT_MAP reg_core0_can_int_map 0 5 read-write USB_INTR_MAP usb intr map register 0x68 0x20 USB_INTR_MAP reg_core0_usb_intr_map 0 5 read-write RTC_CORE_INTR_MAP rtc intr map register 0x6C 0x20 RTC_CORE_INTR_MAP reg_core0_rtc_core_intr_map 0 5 read-write RMT_INTR_MAP rmt intr map register 0x70 0x20 RMT_INTR_MAP reg_core0_rmt_intr_map 0 5 read-write I2C_EXT0_INTR_MAP i2c intr map register 0x74 0x20 I2C_EXT0_INTR_MAP reg_core0_i2c_ext0_intr_map 0 5 read-write TIMER_INT1_MAP timer1 intr map register 0x78 0x20 TIMER_INT1_MAP reg_core0_timer_int1_map 0 5 read-write TIMER_INT2_MAP timer2 intr map register 0x7C 0x20 TIMER_INT2_MAP reg_core0_timer_int2_map 0 5 read-write TG_T0_INT_MAP tg to intr map register 0x80 0x20 TG_T0_INT_MAP reg_core0_tg_t0_int_map 0 5 read-write TG_WDT_INT_MAP tg wdt intr map register 0x84 0x20 TG_WDT_INT_MAP reg_core0_tg_wdt_int_map 0 5 read-write TG1_T0_INT_MAP tg1 to intr map register 0x88 0x20 TG1_T0_INT_MAP reg_core0_tg1_t0_int_map 0 5 read-write TG1_WDT_INT_MAP tg1 wdt intr map register 0x8C 0x20 TG1_WDT_INT_MAP reg_core0_tg1_wdt_int_map 0 5 read-write CACHE_IA_INT_MAP cache ia intr map register 0x90 0x20 CACHE_IA_INT_MAP reg_core0_cache_ia_int_map 0 5 read-write SYSTIMER_TARGET0_INT_MAP systimer intr map register 0x94 0x20 SYSTIMER_TARGET0_INT_MAP reg_core0_systimer_target0_int_map 0 5 read-write SYSTIMER_TARGET1_INT_MAP systimer target1 intr map register 0x98 0x20 SYSTIMER_TARGET1_INT_MAP reg_core0_systimer_target1_int_map 0 5 read-write SYSTIMER_TARGET2_INT_MAP systimer target2 intr map register 0x9C 0x20 SYSTIMER_TARGET2_INT_MAP reg_core0_systimer_target2_int_map 0 5 read-write SPI_MEM_REJECT_INTR_MAP spi mem reject intr map register 0xA0 0x20 SPI_MEM_REJECT_INTR_MAP reg_core0_spi_mem_reject_intr_map 0 5 read-write ICACHE_PRELOAD_INT_MAP icache perload intr map register 0xA4 0x20 ICACHE_PRELOAD_INT_MAP reg_core0_icache_preload_int_map 0 5 read-write ICACHE_SYNC_INT_MAP icache sync intr map register 0xA8 0x20 ICACHE_SYNC_INT_MAP reg_core0_icache_sync_int_map 0 5 read-write APB_ADC_INT_MAP adc intr map register 0xAC 0x20 APB_ADC_INT_MAP reg_core0_apb_adc_int_map 0 5 read-write DMA_CH0_INT_MAP dma ch0 intr map register 0xB0 0x20 DMA_CH0_INT_MAP reg_core0_dma_ch0_int_map 0 5 read-write DMA_CH1_INT_MAP dma ch1 intr map register 0xB4 0x20 DMA_CH1_INT_MAP reg_core0_dma_ch1_int_map 0 5 read-write DMA_CH2_INT_MAP dma ch2 intr map register 0xB8 0x20 DMA_CH2_INT_MAP reg_core0_dma_ch2_int_map 0 5 read-write RSA_INT_MAP rsa intr map register 0xBC 0x20 RSA_INT_MAP reg_core0_rsa_int_map 0 5 read-write AES_INT_MAP aes intr map register 0xC0 0x20 AES_INT_MAP reg_core0_aes_int_map 0 5 read-write SHA_INT_MAP sha intr map register 0xC4 0x20 SHA_INT_MAP reg_core0_sha_int_map 0 5 read-write CPU_INTR_FROM_CPU_0_MAP cpu from cpu 0 intr map register 0xC8 0x20 CPU_INTR_FROM_CPU_0_MAP reg_core0_cpu_intr_from_cpu_0_map 0 5 read-write CPU_INTR_FROM_CPU_1_MAP cpu from cpu 0 intr map register 0xCC 0x20 CPU_INTR_FROM_CPU_1_MAP reg_core0_cpu_intr_from_cpu_1_map 0 5 read-write CPU_INTR_FROM_CPU_2_MAP cpu from cpu 1 intr map register 0xD0 0x20 CPU_INTR_FROM_CPU_2_MAP reg_core0_cpu_intr_from_cpu_2_map 0 5 read-write CPU_INTR_FROM_CPU_3_MAP cpu from cpu 3 intr map register 0xD4 0x20 CPU_INTR_FROM_CPU_3_MAP reg_core0_cpu_intr_from_cpu_3_map 0 5 read-write ASSIST_DEBUG_INTR_MAP assist debug intr map register 0xD8 0x20 ASSIST_DEBUG_INTR_MAP reg_core0_assist_debug_intr_map 0 5 read-write DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP dma pms violatile intr map register 0xDC 0x20 DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP reg_core0_dma_apbperi_pms_monitor_violate_intr_map 0 5 read-write CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP iram0 pms violatile intr map register 0xE0 0x20 CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP reg_core0_core_0_iram0_pms_monitor_violate_intr_map 0 5 read-write CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP mac intr map register 0xE4 0x20 CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP reg_core0_core_0_dram0_pms_monitor_violate_intr_map 0 5 read-write CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP mac intr map register 0xE8 0x20 CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP reg_core0_core_0_pif_pms_monitor_violate_intr_map 0 5 read-write CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP mac intr map register 0xEC 0x20 CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP reg_core0_core_0_pif_pms_monitor_violate_size_intr_map 0 5 read-write BACKUP_PMS_VIOLATE_INTR_MAP mac intr map register 0xF0 0x20 BACKUP_PMS_VIOLATE_INTR_MAP reg_core0_backup_pms_violate_intr_map 0 5 read-write CACHE_CORE0_ACS_INT_MAP mac intr map register 0xF4 0x20 CACHE_CORE0_ACS_INT_MAP reg_core0_cache_core0_acs_int_map 0 5 read-write INTR_STATUS_REG_0 mac intr map register 0xF8 0x20 INTR_STATUS_0 reg_core0_intr_status_0 0 32 read-only INTR_STATUS_REG_1 mac intr map register 0xFC 0x20 INTR_STATUS_1 reg_core0_intr_status_1 0 32 read-only CLOCK_GATE mac intr map register 0x100 0x20 0x00000001 REG_CLK_EN reg_core0_reg_clk_en 0 1 read-write CPU_INT_ENABLE mac intr map register 0x104 0x20 CPU_INT_ENABLE reg_core0_cpu_int_enable 0 32 read-write CPU_INT_TYPE mac intr map register 0x108 0x20 CPU_INT_TYPE reg_core0_cpu_int_type 0 32 read-write CPU_INT_CLEAR mac intr map register 0x10C 0x20 CPU_INT_CLEAR reg_core0_cpu_int_clear 0 32 read-write CPU_INT_EIP_STATUS mac intr map register 0x110 0x20 CPU_INT_EIP_STATUS reg_core0_cpu_int_eip_status 0 32 read-only CPU_INT_PRI_0 mac intr map register 0x114 0x20 CPU_PRI_0_MAP reg_core0_cpu_pri_0_map 0 4 read-write CPU_INT_PRI_1 mac intr map register 0x118 0x20 CPU_PRI_1_MAP reg_core0_cpu_pri_1_map 0 4 read-write CPU_INT_PRI_2 mac intr map register 0x11C 0x20 CPU_PRI_2_MAP reg_core0_cpu_pri_2_map 0 4 read-write CPU_INT_PRI_3 mac intr map register 0x120 0x20 CPU_PRI_3_MAP reg_core0_cpu_pri_3_map 0 4 read-write CPU_INT_PRI_4 mac intr map register 0x124 0x20 CPU_PRI_4_MAP reg_core0_cpu_pri_4_map 0 4 read-write CPU_INT_PRI_5 mac intr map register 0x128 0x20 CPU_PRI_5_MAP reg_core0_cpu_pri_5_map 0 4 read-write CPU_INT_PRI_6 mac intr map register 0x12C 0x20 CPU_PRI_6_MAP reg_core0_cpu_pri_6_map 0 4 read-write CPU_INT_PRI_7 mac intr map register 0x130 0x20 CPU_PRI_7_MAP reg_core0_cpu_pri_7_map 0 4 read-write CPU_INT_PRI_8 mac intr map register 0x134 0x20 CPU_PRI_8_MAP reg_core0_cpu_pri_8_map 0 4 read-write CPU_INT_PRI_9 mac intr map register 0x138 0x20 CPU_PRI_9_MAP reg_core0_cpu_pri_9_map 0 4 read-write CPU_INT_PRI_10 mac intr map register 0x13C 0x20 CPU_PRI_10_MAP reg_core0_cpu_pri_10_map 0 4 read-write CPU_INT_PRI_11 mac intr map register 0x140 0x20 CPU_PRI_11_MAP reg_core0_cpu_pri_11_map 0 4 read-write CPU_INT_PRI_12 mac intr map register 0x144 0x20 CPU_PRI_12_MAP reg_core0_cpu_pri_12_map 0 4 read-write CPU_INT_PRI_13 mac intr map register 0x148 0x20 CPU_PRI_13_MAP reg_core0_cpu_pri_13_map 0 4 read-write CPU_INT_PRI_14 mac intr map register 0x14C 0x20 CPU_PRI_14_MAP reg_core0_cpu_pri_14_map 0 4 read-write CPU_INT_PRI_15 mac intr map register 0x150 0x20 CPU_PRI_15_MAP reg_core0_cpu_pri_15_map 0 4 read-write CPU_INT_PRI_16 mac intr map register 0x154 0x20 CPU_PRI_16_MAP reg_core0_cpu_pri_16_map 0 4 read-write CPU_INT_PRI_17 mac intr map register 0x158 0x20 CPU_PRI_17_MAP reg_core0_cpu_pri_17_map 0 4 read-write CPU_INT_PRI_18 mac intr map register 0x15C 0x20 CPU_PRI_18_MAP reg_core0_cpu_pri_18_map 0 4 read-write CPU_INT_PRI_19 mac intr map register 0x160 0x20 CPU_PRI_19_MAP reg_core0_cpu_pri_19_map 0 4 read-write CPU_INT_PRI_20 mac intr map register 0x164 0x20 CPU_PRI_20_MAP reg_core0_cpu_pri_20_map 0 4 read-write CPU_INT_PRI_21 mac intr map register 0x168 0x20 CPU_PRI_21_MAP reg_core0_cpu_pri_21_map 0 4 read-write CPU_INT_PRI_22 mac intr map register 0x16C 0x20 CPU_PRI_22_MAP reg_core0_cpu_pri_22_map 0 4 read-write CPU_INT_PRI_23 mac intr map register 0x170 0x20 CPU_PRI_23_MAP reg_core0_cpu_pri_23_map 0 4 read-write CPU_INT_PRI_24 mac intr map register 0x174 0x20 CPU_PRI_24_MAP reg_core0_cpu_pri_24_map 0 4 read-write CPU_INT_PRI_25 mac intr map register 0x178 0x20 CPU_PRI_25_MAP reg_core0_cpu_pri_25_map 0 4 read-write CPU_INT_PRI_26 mac intr map register 0x17C 0x20 CPU_PRI_26_MAP reg_core0_cpu_pri_26_map 0 4 read-write CPU_INT_PRI_27 mac intr map register 0x180 0x20 CPU_PRI_27_MAP reg_core0_cpu_pri_27_map 0 4 read-write CPU_INT_PRI_28 mac intr map register 0x184 0x20 CPU_PRI_28_MAP reg_core0_cpu_pri_28_map 0 4 read-write CPU_INT_PRI_29 mac intr map register 0x188 0x20 CPU_PRI_29_MAP reg_core0_cpu_pri_29_map 0 4 read-write CPU_INT_PRI_30 mac intr map register 0x18C 0x20 CPU_PRI_30_MAP reg_core0_cpu_pri_30_map 0 4 read-write CPU_INT_PRI_31 mac intr map register 0x190 0x20 CPU_PRI_31_MAP reg_core0_cpu_pri_31_map 0 4 read-write CPU_INT_THRESH mac intr map register 0x194 0x20 CPU_INT_THRESH reg_core0_cpu_int_thresh 0 4 read-write INTERRUPT_REG_DATE mac intr map register 0x7FC 0x20 0x02007210 INTERRUPT_REG_DATE reg_core0_interrupt_reg_date 0 28 read-write IO_MUX Input/Output Multiplexer IO_MUX 0x60009000 0x0 0x60 registers PIN_CTRL Clock Output Configuration Register 0x0 0x20 0x000007FF CLK_OUT1 If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. 0 4 read-write CLK_OUT2 If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. 4 4 read-write CLK_OUT3 If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. 8 4 read-write 22 0x4 GPIO%s IO MUX Configure Register for pad XTAL_32K_P 0x4 0x20 0x00000B00 MCU_OE Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. 1 1 read-write MCU_WPD Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. 15 1 read-write DATE IO MUX Version Control Register 0xFC 0x20 0x02006050 REG_DATE Version control register 0 28 read-write LEDC LED Control PWM (Pulse Width Modulation) LEDC 0x60019000 0x0 0xB0 registers LEDC 23 6 0x14 0-5 CH%s_CONF0 LEDC_LSCH%s_CONF%s. 0x0 0x20 TIMER_SEL reg_timer_sel_lsch0. 0 2 read-write SIG_OUT_EN reg_sig_out_en_lsch0. 2 1 read-write IDLE_LV reg_idle_lv_lsch0. 3 1 read-write PARA_UP reg_para_up_lsch0. 4 1 write-only OVF_NUM reg_ovf_num_lsch0. 5 10 read-write OVF_CNT_EN reg_ovf_cnt_en_lsch0. 15 1 read-write OVF_CNT_RESET reg_ovf_cnt_reset_lsch0. 16 1 write-only 6 0x14 0-5 CH%s_HPOINT LEDC_LSCH%s_HPOINT. 0x4 0x20 HPOINT reg_hpoint_lsch0. 0 14 read-write 6 0x14 0-5 CH%s_DUTY LEDC_LSCH%s_DUTY. 0x8 0x20 DUTY reg_duty_lsch0. 0 19 read-write 6 0x14 0-5 CH%s_CONF1 LEDC_LSCH%s_CONF1. 0xC 0x20 0x40000000 DUTY_SCALE reg_duty_scale_lsch0. 0 10 read-write DUTY_CYCLE reg_duty_cycle_lsch0. 10 10 read-write DUTY_NUM reg_duty_num_lsch0. 20 10 read-write DUTY_INC reg_duty_inc_lsch0. 30 1 read-write DUTY_START reg_duty_start_lsch0. 31 1 read-write 6 0x14 0-5 CH%s_DUTY_R LEDC_LSCH%s_DUTY_R. 0x10 0x20 DUTY_R reg_duty_lsch0_r. 0 19 read-only 4 0x8 0-3 TIMER%s_CONF LEDC_LSTIMER%s_CONF. 0xA0 0x20 0x00800000 DUTY_RES reg_lstimer0_duty_res. 0 4 read-write CLK_DIV reg_clk_div_lstimer0. 4 18 read-write PAUSE reg_lstimer0_pause. 22 1 read-write RST reg_lstimer0_rst. 23 1 read-write TICK_SEL reg_tick_sel_lstimer0. 24 1 read-write PARA_UP reg_lstimer0_para_up. 25 1 write-only 4 0x8 0-3 TIMER%s_VALUE LEDC_LSTIMER%s_VALUE. 0xA4 0x20 CNT reg_lstimer0_cnt. 0 14 read-only INT_RAW LEDC_INT_RAW. 0xC0 0x20 LSTIMER0_OVF_INT_RAW reg_lstimer0_ovf_int_raw. 0 1 read-only LSTIMER1_OVF_INT_RAW reg_lstimer1_ovf_int_raw. 1 1 read-only LSTIMER2_OVF_INT_RAW reg_lstimer2_ovf_int_raw. 2 1 read-only LSTIMER3_OVF_INT_RAW reg_lstimer3_ovf_int_raw. 3 1 read-only DUTY_CHNG_END_LSCH0_INT_RAW reg_duty_chng_end_lsch0_int_raw. 4 1 read-only DUTY_CHNG_END_LSCH1_INT_RAW reg_duty_chng_end_lsch1_int_raw. 5 1 read-only DUTY_CHNG_END_LSCH2_INT_RAW reg_duty_chng_end_lsch2_int_raw. 6 1 read-only DUTY_CHNG_END_LSCH3_INT_RAW reg_duty_chng_end_lsch3_int_raw. 7 1 read-only DUTY_CHNG_END_LSCH4_INT_RAW reg_duty_chng_end_lsch4_int_raw. 8 1 read-only DUTY_CHNG_END_LSCH5_INT_RAW reg_duty_chng_end_lsch5_int_raw. 9 1 read-only OVF_CNT_LSCH0_INT_RAW reg_ovf_cnt_lsch0_int_raw. 10 1 read-only OVF_CNT_LSCH1_INT_RAW reg_ovf_cnt_lsch1_int_raw. 11 1 read-only OVF_CNT_LSCH2_INT_RAW reg_ovf_cnt_lsch2_int_raw. 12 1 read-only OVF_CNT_LSCH3_INT_RAW reg_ovf_cnt_lsch3_int_raw. 13 1 read-only OVF_CNT_LSCH4_INT_RAW reg_ovf_cnt_lsch4_int_raw. 14 1 read-only OVF_CNT_LSCH5_INT_RAW reg_ovf_cnt_lsch5_int_raw. 15 1 read-only INT_ST LEDC_INT_ST. 0xC4 0x20 LSTIMER0_OVF_INT_ST reg_lstimer0_ovf_int_st. 0 1 read-only LSTIMER1_OVF_INT_ST reg_lstimer1_ovf_int_st. 1 1 read-only LSTIMER2_OVF_INT_ST reg_lstimer2_ovf_int_st. 2 1 read-only LSTIMER3_OVF_INT_ST reg_lstimer3_ovf_int_st. 3 1 read-only DUTY_CHNG_END_LSCH0_INT_ST reg_duty_chng_end_lsch0_int_st. 4 1 read-only DUTY_CHNG_END_LSCH1_INT_ST reg_duty_chng_end_lsch1_int_st. 5 1 read-only DUTY_CHNG_END_LSCH2_INT_ST reg_duty_chng_end_lsch2_int_st. 6 1 read-only DUTY_CHNG_END_LSCH3_INT_ST reg_duty_chng_end_lsch3_int_st. 7 1 read-only DUTY_CHNG_END_LSCH4_INT_ST reg_duty_chng_end_lsch4_int_st. 8 1 read-only DUTY_CHNG_END_LSCH5_INT_ST reg_duty_chng_end_lsch5_int_st. 9 1 read-only OVF_CNT_LSCH0_INT_ST reg_ovf_cnt_lsch0_int_st. 10 1 read-only OVF_CNT_LSCH1_INT_ST reg_ovf_cnt_lsch1_int_st. 11 1 read-only OVF_CNT_LSCH2_INT_ST reg_ovf_cnt_lsch2_int_st. 12 1 read-only OVF_CNT_LSCH3_INT_ST reg_ovf_cnt_lsch3_int_st. 13 1 read-only OVF_CNT_LSCH4_INT_ST reg_ovf_cnt_lsch4_int_st. 14 1 read-only OVF_CNT_LSCH5_INT_ST reg_ovf_cnt_lsch5_int_st. 15 1 read-only INT_ENA LEDC_INT_ENA. 0xC8 0x20 LSTIMER0_OVF_INT_ENA reg_lstimer0_ovf_int_ena. 0 1 read-write LSTIMER1_OVF_INT_ENA reg_lstimer1_ovf_int_ena. 1 1 read-write LSTIMER2_OVF_INT_ENA reg_lstimer2_ovf_int_ena. 2 1 read-write LSTIMER3_OVF_INT_ENA reg_lstimer3_ovf_int_ena. 3 1 read-write DUTY_CHNG_END_LSCH0_INT_ENA reg_duty_chng_end_lsch0_int_ena. 4 1 read-write DUTY_CHNG_END_LSCH1_INT_ENA reg_duty_chng_end_lsch1_int_ena. 5 1 read-write DUTY_CHNG_END_LSCH2_INT_ENA reg_duty_chng_end_lsch2_int_ena. 6 1 read-write DUTY_CHNG_END_LSCH3_INT_ENA reg_duty_chng_end_lsch3_int_ena. 7 1 read-write DUTY_CHNG_END_LSCH4_INT_ENA reg_duty_chng_end_lsch4_int_ena. 8 1 read-write DUTY_CHNG_END_LSCH5_INT_ENA reg_duty_chng_end_lsch5_int_ena. 9 1 read-write OVF_CNT_LSCH0_INT_ENA reg_ovf_cnt_lsch0_int_ena. 10 1 read-write OVF_CNT_LSCH1_INT_ENA reg_ovf_cnt_lsch1_int_ena. 11 1 read-write OVF_CNT_LSCH2_INT_ENA reg_ovf_cnt_lsch2_int_ena. 12 1 read-write OVF_CNT_LSCH3_INT_ENA reg_ovf_cnt_lsch3_int_ena. 13 1 read-write OVF_CNT_LSCH4_INT_ENA reg_ovf_cnt_lsch4_int_ena. 14 1 read-write OVF_CNT_LSCH5_INT_ENA reg_ovf_cnt_lsch5_int_ena. 15 1 read-write INT_CLR LEDC_INT_CLR. 0xCC 0x20 LSTIMER0_OVF_INT_CLR reg_lstimer0_ovf_int_clr. 0 1 write-only LSTIMER1_OVF_INT_CLR reg_lstimer1_ovf_int_clr. 1 1 write-only LSTIMER2_OVF_INT_CLR reg_lstimer2_ovf_int_clr. 2 1 write-only LSTIMER3_OVF_INT_CLR reg_lstimer3_ovf_int_clr. 3 1 write-only DUTY_CHNG_END_LSCH0_INT_CLR reg_duty_chng_end_lsch0_int_clr. 4 1 write-only DUTY_CHNG_END_LSCH1_INT_CLR reg_duty_chng_end_lsch1_int_clr. 5 1 write-only DUTY_CHNG_END_LSCH2_INT_CLR reg_duty_chng_end_lsch2_int_clr. 6 1 write-only DUTY_CHNG_END_LSCH3_INT_CLR reg_duty_chng_end_lsch3_int_clr. 7 1 write-only DUTY_CHNG_END_LSCH4_INT_CLR reg_duty_chng_end_lsch4_int_clr. 8 1 write-only DUTY_CHNG_END_LSCH5_INT_CLR reg_duty_chng_end_lsch5_int_clr. 9 1 write-only OVF_CNT_LSCH0_INT_CLR reg_ovf_cnt_lsch0_int_clr. 10 1 write-only OVF_CNT_LSCH1_INT_CLR reg_ovf_cnt_lsch1_int_clr. 11 1 write-only OVF_CNT_LSCH2_INT_CLR reg_ovf_cnt_lsch2_int_clr. 12 1 write-only OVF_CNT_LSCH3_INT_CLR reg_ovf_cnt_lsch3_int_clr. 13 1 write-only OVF_CNT_LSCH4_INT_CLR reg_ovf_cnt_lsch4_int_clr. 14 1 write-only OVF_CNT_LSCH5_INT_CLR reg_ovf_cnt_lsch5_int_clr. 15 1 write-only CONF LEDC_CONF. 0xD0 0x20 APB_CLK_SEL reg_apb_clk_sel. 0 2 read-write CLK_EN reg_clk_en. 31 1 read-write DATE LEDC_DATE. 0xFC 0x20 0x19061700 LEDC_DATE reg_ledc_date. 0 32 read-write RMT Remote Control Peripheral RMT 0x60016000 0x0 0x78 registers RMT 28 CH0DATA RMT_CH0DATA_REG. 0x0 0x20 DATA Reserved. 0 32 read-write CH1DATA RMT_CH1DATA_REG. 0x4 0x20 DATA Reserved. 0 32 read-write CH2DATA RMT_CH2DATA_REG. 0x8 0x20 DATA Reserved. 0 32 read-write CH3DATA RMT_CH3DATA_REG. 0xC 0x20 DATA Reserved. 0 32 read-write 2 0x4 0-1 CH%s_TX_CONF0 RMT_CH%sCONF%s_REG. 0x10 0x20 0x00710200 TX_START reg_tx_start_ch0. 0 1 write-only MEM_RD_RST reg_mem_rd_rst_ch0. 1 1 write-only APB_MEM_RST reg_apb_mem_rst_ch0. 2 1 write-only TX_CONTI_MODE reg_tx_conti_mode_ch0. 3 1 read-write MEM_TX_WRAP_EN reg_mem_tx_wrap_en_ch0. 4 1 read-write IDLE_OUT_LV reg_idle_out_lv_ch0. 5 1 read-write IDLE_OUT_EN reg_idle_out_en_ch0. 6 1 read-write TX_STOP reg_tx_stop_ch0. 7 1 read-write DIV_CNT reg_div_cnt_ch0. 8 8 read-write MEM_SIZE reg_mem_size_ch0. 16 3 read-write CARRIER_EFF_EN reg_carrier_eff_en_ch0. 20 1 read-write CARRIER_EN reg_carrier_en_ch0. 21 1 read-write CARRIER_OUT_LV reg_carrier_out_lv_ch0. 22 1 read-write AFIFO_RST reg_afifo_rst_ch0. 23 1 write-only CONF_UPDATE reg_reg_conf_update_ch0. 24 1 write-only 2 0x8 2-3 CH%s_RX_CONF0 RMT_CH2CONF0_REG. 0x18 0x20 0x30FFFF02 DIV_CNT reg_div_cnt_ch2. 0 8 read-write IDLE_THRES reg_idle_thres_ch2. 8 15 read-write MEM_SIZE reg_mem_size_ch2. 23 3 read-write CARRIER_EN reg_carrier_en_ch2. 28 1 read-write CARRIER_OUT_LV reg_carrier_out_lv_ch2. 29 1 read-write CH2CONF1 RMT_CH2CONF1_REG. 0x1C 0x20 0x000001E8 RX_EN reg_rx_en_ch2. 0 1 read-write MEM_WR_RST reg_mem_wr_rst_ch2. 1 1 write-only APB_MEM_RST reg_apb_mem_rst_ch2. 2 1 write-only MEM_OWNER reg_mem_owner_ch2. 3 1 read-write RX_FILTER_EN reg_rx_filter_en_ch2. 4 1 read-write RX_FILTER_THRES reg_rx_filter_thres_ch2. 5 8 read-write MEM_RX_WRAP_EN reg_mem_rx_wrap_en_ch2. 13 1 read-write AFIFO_RST reg_afifo_rst_ch2. 14 1 write-only CONF_UPDATE reg_conf_update_ch2. 15 1 write-only CH3CONF1 RMT_CH3CONF1_REG. 0x24 0x20 0x000001E8 RX_EN reg_rx_en_ch3. 0 1 read-write MEM_WR_RST reg_mem_wr_rst_ch3. 1 1 write-only APB_MEM_RST reg_apb_mem_rst_ch3. 2 1 write-only MEM_OWNER reg_mem_owner_ch3. 3 1 read-write RX_FILTER_EN reg_rx_filter_en_ch3. 4 1 read-write RX_FILTER_THRES reg_rx_filter_thres_ch3. 5 8 read-write MEM_RX_WRAP_EN reg_mem_rx_wrap_en_ch3. 13 1 read-write AFIFO_RST reg_afifo_rst_ch3. 14 1 write-only CONF_UPDATE reg_conf_update_ch3. 15 1 write-only CH0STATUS RMT_CH0STATUS_REG. 0x28 0x20 MEM_RADDR_EX reg_mem_raddr_ex_ch0. 0 9 read-only STATE reg_state_ch0. 9 3 read-only APB_MEM_WADDR reg_apb_mem_waddr_ch0. 12 9 read-only APB_MEM_RD_ERR reg_apb_mem_rd_err_ch0. 21 1 read-only MEM_EMPTY reg_mem_empty_ch0. 22 1 read-only APB_MEM_WR_ERR reg_apb_mem_wr_err_ch0. 23 1 read-only APB_MEM_RADDR reg_apb_mem_raddr_ch0. 24 8 read-only CH1STATUS RMT_CH1STATUS_REG. 0x2C 0x20 MEM_RADDR_EX reg_mem_raddr_ex_ch1. 0 9 read-only STATE reg_state_ch1. 9 3 read-only APB_MEM_WADDR reg_apb_mem_waddr_ch1. 12 9 read-only APB_MEM_RD_ERR reg_apb_mem_rd_err_ch1. 21 1 read-only MEM_EMPTY reg_mem_empty_ch1. 22 1 read-only APB_MEM_WR_ERR reg_apb_mem_wr_err_ch1. 23 1 read-only APB_MEM_RADDR reg_apb_mem_raddr_ch1. 24 8 read-only CH2STATUS RMT_CH2STATUS_REG. 0x30 0x20 MEM_WADDR_EX reg_mem_waddr_ex_ch2. 0 9 read-only APB_MEM_RADDR reg_apb_mem_raddr_ch2. 12 9 read-only STATE reg_state_ch2. 22 3 read-only MEM_OWNER_ERR reg_mem_owner_err_ch2. 25 1 read-only MEM_FULL reg_mem_full_ch2. 26 1 read-only APB_MEM_RD_ERR reg_apb_mem_rd_err_ch2. 27 1 read-only CH3STATUS RMT_CH3STATUS_REG. 0x34 0x20 MEM_WADDR_EX reg_mem_waddr_ex_ch3. 0 9 read-only APB_MEM_RADDR reg_apb_mem_raddr_ch3. 12 9 read-only STATE reg_state_ch3. 22 3 read-only MEM_OWNER_ERR reg_mem_owner_err_ch3. 25 1 read-only MEM_FULL reg_mem_full_ch3. 26 1 read-only APB_MEM_RD_ERR reg_apb_mem_rd_err_ch3. 27 1 read-only INT_RAW RMT_INT_RAW_REG. 0x38 0x20 2 0x1 0-1 CH%s_TX_END_INT_RAW reg_ch%s_tx_end_int_raw. 0 1 read-only 2 0x1 2-3 CH%s_RX_END_INT_RAW reg_ch2_rx_end_int_raw. 2 1 read-only 2 0x1 0-1 CH%s_TX_ERR_INT_RAW reg_ch%s_err_int_raw. 4 1 read-only 2 0x1 2-3 CH%s_RX_ERR_INT_RAW reg_ch2_err_int_raw. 6 1 read-only 2 0x1 0-1 CH%s_TX_THR_EVENT_INT_RAW reg_ch%s_tx_thr_event_int_raw. 8 1 read-only CH2_RX_THR_EVENT_INT_RAW reg_ch2_rx_thr_event_int_raw. 10 1 read-only CH3_RX_THR_EVENT_INT_RAW reg_ch3_rx_thr_event_int_raw. 11 1 read-only 2 0x1 0-1 CH%s_TX_LOOP_INT_RAW reg_ch%s_tx_loop_int_raw. 12 1 read-only INT_ST RMT_INT_ST_REG. 0x3C 0x20 2 0x1 0-1 CH%s_TX_END_INT_ST reg_ch%s_tx_end_int_st. 0 1 read-only 2 0x1 2-3 CH%s_RX_END_INT_ST reg_ch2_rx_end_int_st. 2 1 read-only 2 0x1 0-1 CH%s_TX_ERR_INT_ST reg_ch%s_err_int_st. 4 1 read-only 2 0x1 2-3 CH%s_RX_ERR_INT_ST reg_ch2_err_int_st. 6 1 read-only 2 0x1 0-1 CH%s_TX_THR_EVENT_INT_ST reg_ch%s_tx_thr_event_int_st. 8 1 read-only CH2_RX_THR_EVENT_INT_ST reg_ch2_rx_thr_event_int_st. 10 1 read-only CH3_RX_THR_EVENT_INT_ST reg_ch3_rx_thr_event_int_st. 11 1 read-only 2 0x1 0-1 CH%s_TX_LOOP_INT_ST reg_ch%s_tx_loop_int_st. 12 1 read-only INT_ENA RMT_INT_ENA_REG. 0x40 0x20 2 0x1 0-1 CH%s_TX_END_INT_ENA reg_ch%s_tx_end_int_ena. 0 1 read-write 2 0x1 2-3 CH%s_RX_END_INT_ENA reg_ch2_rx_end_int_ena. 2 1 read-write 2 0x1 0-1 CH%s_TX_ERR_INT_ENA reg_ch%s_err_int_ena. 4 1 read-write 2 0x1 2-3 CH%s_RX_ERR_INT_ENA reg_ch2_err_int_ena. 6 1 read-write 2 0x1 0-1 CH%s_TX_THR_EVENT_INT_ENA reg_ch%s_tx_thr_event_int_ena. 8 1 read-write CH2_RX_THR_EVENT_INT_ENA reg_ch2_rx_thr_event_int_ena. 10 1 read-write CH3_RX_THR_EVENT_INT_ENA reg_ch3_rx_thr_event_int_ena. 11 1 read-write 2 0x1 0-1 CH%s_TX_LOOP_INT_ENA reg_ch%s_tx_loop_int_ena. 12 1 read-write INT_CLR RMT_INT_CLR_REG. 0x44 0x20 2 0x1 0-1 CH%s_TX_END_INT_CLR reg_ch%s_tx_end_int_clr. 0 1 write-only 2 0x1 2-3 CH%s_RX_END_INT_CLR reg_ch2_rx_end_int_clr. 2 1 write-only 2 0x1 0-1 CH%s_TX_ERR_INT_CLR reg_ch%s_err_int_clr. 4 1 write-only 2 0x1 2-3 CH%s_RX_ERR_INT_CLR reg_ch2_err_int_clr. 6 1 write-only 2 0x1 0-1 CH%s_TX_THR_EVENT_INT_CLR reg_ch%s_tx_thr_event_int_clr. 8 1 write-only CH2_RX_THR_EVENT_INT_CLR reg_ch2_rx_thr_event_int_clr. 10 1 write-only CH3_RX_THR_EVENT_INT_CLR reg_ch3_rx_thr_event_int_clr. 11 1 write-only 2 0x1 0-1 CH%s_TX_LOOP_INT_CLR reg_ch%s_tx_loop_int_clr. 12 1 write-only CH0CARRIER_DUTY RMT_CH0CARRIER_DUTY_REG. 0x48 0x20 0x00400040 CARRIER_LOW reg_carrier_low_ch0. 0 16 read-write CARRIER_HIGH reg_carrier_high_ch0. 16 16 read-write CH1CARRIER_DUTY RMT_CH1CARRIER_DUTY_REG. 0x4C 0x20 0x00400040 CARRIER_LOW reg_carrier_low_ch1. 0 16 read-write CARRIER_HIGH reg_carrier_high_ch1. 16 16 read-write CH2_RX_CARRIER_RM RMT_CH2_RX_CARRIER_RM_REG. 0x50 0x20 CARRIER_LOW_THRES reg_carrier_low_thres_ch2. 0 16 read-write CARRIER_HIGH_THRES reg_carrier_high_thres_ch2. 16 16 read-write CH3_RX_CARRIER_RM RMT_CH3_RX_CARRIER_RM_REG. 0x54 0x20 CARRIER_LOW_THRES reg_carrier_low_thres_ch3. 0 16 read-write CARRIER_HIGH_THRES reg_carrier_high_thres_ch3. 16 16 read-write 2 0x4 0-1 CH%s_TX_LIM RMT_CH%s_TX_LIM_REG. 0x58 0x20 0x00000080 TX_LIM reg_rmt_tx_lim_ch0. 0 9 read-write TX_LOOP_NUM reg_rmt_tx_loop_num_ch0. 9 10 read-write TX_LOOP_CNT_EN reg_rmt_tx_loop_cnt_en_ch0. 19 1 read-write LOOP_COUNT_RESET reg_loop_count_reset_ch0. 20 1 write-only 2 0x4 2-3 CH%s_RX_LIM RMT_CH2_RX_LIM_REG. 0x60 0x20 0x00000080 RX_LIM reg_rmt_rx_lim_ch2. 0 9 read-write SYS_CONF RMT_SYS_CONF_REG. 0x68 0x20 0x05000010 APB_FIFO_MASK reg_apb_fifo_mask. 0 1 read-write MEM_CLK_FORCE_ON reg_mem_clk_force_on. 1 1 read-write MEM_FORCE_PD reg_rmt_mem_force_pd. 2 1 read-write MEM_FORCE_PU reg_rmt_mem_force_pu. 3 1 read-write SCLK_DIV_NUM reg_rmt_sclk_div_num. 4 8 read-write SCLK_DIV_A reg_rmt_sclk_div_a. 12 6 read-write SCLK_DIV_B reg_rmt_sclk_div_b. 18 6 read-write SCLK_SEL reg_rmt_sclk_sel. 24 2 read-write SCLK_ACTIVE reg_rmt_sclk_active. 26 1 read-write CLK_EN reg_clk_en. 31 1 read-write TX_SIM RMT_TX_SIM_REG. 0x6C 0x20 TX_SIM_CH0 reg_rmt_tx_sim_ch0. 0 1 read-write TX_SIM_CH1 reg_rmt_tx_sim_ch1. 1 1 read-write TX_SIM_EN reg_rmt_tx_sim_en. 2 1 read-write REF_CNT_RST RMT_REF_CNT_RST_REG. 0x70 0x20 CH0 reg_ref_cnt_rst_ch0. 0 1 write-only CH1 reg_ref_cnt_rst_ch1. 1 1 write-only CH2 reg_ref_cnt_rst_ch2. 2 1 write-only CH3 reg_ref_cnt_rst_ch3. 3 1 write-only DATE RMT_DATE_REG. 0xCC 0x20 0x02006231 DATE reg_rmt_date. 0 28 read-write RNG Hardware random number generator RNG 0x60026000 0x0 0x4 registers DATA Random number data 0xB0 0x20 RSA RSA (Rivest Shamir Adleman) Accelerator RSA 0x6003C000 0x0 0x74 registers RSA 47 16 0x1 M_MEM[%s] The memory that stores M 0x0 0x8 16 0x1 Z_MEM[%s] The memory that stores Z 0x200 0x8 16 0x1 Y_MEM[%s] The memory that stores Y 0x400 0x8 16 0x1 X_MEM[%s] The memory that stores X 0x600 0x8 M_PRIME RSA M_prime register 0x800 0x20 M_PRIME Those bits stores m' 0 32 read-write MODE RSA mode register 0x804 0x20 MODE rsa mode (rsa length). 0 7 read-write QUERY_CLEAN RSA query clean register 0x808 0x20 QUERY_CLEAN query clean 0 1 read-only SET_START_MODEXP RSA modular exponentiation trigger register. 0x80C 0x20 SET_START_MODEXP start modular exponentiation 0 1 write-only SET_START_MODMULT RSA modular multiplication trigger register. 0x810 0x20 SET_START_MODMULT start modular multiplication 0 1 write-only SET_START_MULT RSA normal multiplication trigger register. 0x814 0x20 SET_START_MULT start multiplicaiton 0 1 write-only QUERY_IDLE RSA query idle register 0x818 0x20 QUERY_IDLE query rsa idle. 1'b0: busy, 1'b1: idle 0 1 read-only INT_CLR RSA interrupt clear register 0x81C 0x20 CLEAR_INTERRUPT set this bit to clear RSA interrupt. 0 1 write-only CONSTANT_TIME RSA constant time option register 0x820 0x20 0x00000001 CONSTANT_TIME Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut). 0 1 read-write SEARCH_ENABLE RSA search option 0x824 0x20 SEARCH_ENABLE Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS. 0 1 read-write SEARCH_POS RSA search position configure register 0x828 0x20 SEARCH_POS Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. 0 12 read-write INT_ENA RSA interrupt enable register 0x82C 0x20 INT_ENA Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default). 0 1 read-write DATE RSA version control register 0x830 0x20 0x20200618 DATE rsa version information 0 30 read-write RTC_CNTL Real-Time Clock Control RTC_CNTL 0x60008000 0x0 0x12C registers RTC_CORE 27 OPTIONS0 rtc configure register 0x0 0x20 0x1C00A000 SW_STALL_APPCPU_C0 {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU 0 2 read-write SW_STALL_PROCPU_C0 {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU 2 2 read-write SW_APPCPU_RST APP CPU SW reset 4 1 write-only SW_PROCPU_RST PRO CPU SW reset 5 1 write-only BB_I2C_FORCE_PD BB_I2C force power down 6 1 read-write BB_I2C_FORCE_PU BB_I2C force power up 7 1 read-write BBPLL_I2C_FORCE_PD BB_PLL _I2C force power down 8 1 read-write BBPLL_I2C_FORCE_PU BB_PLL_I2C force power up 9 1 read-write BBPLL_FORCE_PD BB_PLL force power down 10 1 read-write BBPLL_FORCE_PU BB_PLL force power up 11 1 read-write XTL_FORCE_PD crystall force power down 12 1 read-write XTL_FORCE_PU crystall force power up 13 1 read-write XTL_EN_WAIT wait bias_sleep and current source wakeup 14 4 read-write XTL_EXT_CTR_SEL analog configure 20 3 read-write XTL_FORCE_ISO analog configure 23 1 read-write PLL_FORCE_ISO analog configure 24 1 read-write ANALOG_FORCE_ISO analog configure 25 1 read-write XTL_FORCE_NOISO analog configure 26 1 read-write PLL_FORCE_NOISO analog configure 27 1 read-write ANALOG_FORCE_NOISO analog configure 28 1 read-write DG_WRAP_FORCE_RST digital wrap force reset in deep sleep 29 1 read-write DG_WRAP_FORCE_NORST digital core force no reset in deep sleep 30 1 read-write SW_SYS_RST SW system reset 31 1 write-only SLP_TIMER0 rtc configure register 0x4 0x20 SLP_VAL_LO configure the sleep time 0 32 read-write SLP_TIMER1 rtc configure register 0x8 0x20 SLP_VAL_HI RTC sleep timer high 16 bits 0 16 read-write MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 write-only TIME_UPDATE rtc configure register 0xC 0x20 TIMER_SYS_STALL Enable to record system stall time 27 1 read-write TIMER_XTL_OFF Enable to record 40M XTAL OFF time 28 1 read-write TIMER_SYS_RST enable to record system reset time 29 1 read-write TIME_UPDATE Set 1: to update register with RTC timer 31 1 write-only TIME_LOW0 rtc configure register 0x10 0x20 TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 read-only TIME_HIGH0 rtc configure register 0x14 0x20 TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 read-only STATE0 rtc configure register 0x18 0x20 SW_CPU_INT rtc software interrupt to main cpu 0 1 write-only SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 write-only APB2RTC_BRIDGE_SEL 1: APB to RTC using bridge 22 1 read-write SDIO_ACTIVE_IND SDIO active indication 28 1 read-only SLP_WAKEUP leep wakeup bit 29 1 read-write SLP_REJECT leep reject bit 30 1 read-write SLEEP_EN sleep enable bit 31 1 read-write TIMER1 rtc configure register 0x1C 0x20 0x28140403 CPU_STALL_EN CPU stall enable bit 0 1 read-write CPU_STALL_WAIT CPU stall wait cycles in fast_clk_rtc 1 5 read-write CK8M_WAIT CK8M wait cycles in slow_clk_rtc 6 8 read-write XTL_BUF_WAIT XTAL wait cycles in slow_clk_rtc 14 10 read-write PLL_BUF_WAIT PLL wait cycles in slow_clk_rtc 24 8 read-write TIMER2 rtc configure register 0x20 0x20 0x01000000 MIN_TIME_CK8M_OFF minimal cycles in slow_clk_rtc for CK8M in power down state 24 8 read-write TIMER3 rtc configure register 0x24 0x20 0x0A080A08 WIFI_WAIT_TIMER wifi power domain wakeup time 0 9 read-write WIFI_POWERUP_TIMER wifi power domain power on time 9 7 read-write BT_WAIT_TIMER bt power domain wakeup time 16 9 read-write BT_POWERUP_TIMER bt power domain power on time 25 7 read-write TIMER4 rtc configure register 0x28 0x20 0x10200A08 CPU_TOP_WAIT_TIMER cpu top power domain wakeup time 0 9 read-write CPU_TOP_POWERUP_TIMER cpu top power domain power on time 9 7 read-write DG_WRAP_WAIT_TIMER digital wrap power domain wakeup time 16 9 read-write DG_WRAP_POWERUP_TIMER digital wrap power domain power on time 25 7 read-write TIMER5 rtc configure register 0x2C 0x20 0x00008000 MIN_SLP_VAL minimal sleep cycles in slow_clk_rtc 8 8 read-write TIMER6 rtc configure register 0x30 0x20 0x0A080000 DG_PERI_WAIT_TIMER digital peri power domain wakeup time 16 9 read-write DG_PERI_POWERUP_TIMER digital peri power domain power on time 25 7 read-write ANA_CONF rtc configure register 0x34 0x20 0x00C40000 RESET_POR_FORCE_PD force no bypass i2c power on reset 18 1 read-write RESET_POR_FORCE_PU force bypass i2c power on reset 19 1 read-write GLITCH_RST_EN enable glitch reset 20 1 read-write SAR_I2C_PU PLLA force power up 22 1 read-write PLLA_FORCE_PD PLLA force power down 23 1 read-write PLLA_FORCE_PU PLLA force power up 24 1 read-write BBPLL_CAL_SLP_START start BBPLL calibration during sleep 25 1 read-write PVTMON_PU 1: PVTMON power up 26 1 read-write TXRF_I2C_PU 1: TXRF_I2C power up 27 1 read-write RFRX_PBUS_PU 1: RFRX_PBUS power up 28 1 read-write CKGEN_I2C_PU 1: CKGEN_I2C power up 30 1 read-write PLL_I2C_PU power up pll i2c 31 1 read-write RESET_STATE rtc configure register 0x38 0x20 0x00003000 RESET_CAUSE_PROCPU reset cause of PRO CPU 0 6 read-only RESET_CAUSE_APPCPU reset cause of APP CPU 6 6 read-only STAT_VECTOR_SEL_APPCPU APP CPU state vector sel 12 1 read-write STAT_VECTOR_SEL_PROCPU PRO CPU state vector sel 13 1 read-write ALL_RESET_FLAG_PROCPU PRO CPU reset_flag 14 1 read-only ALL_RESET_FLAG_APPCPU APP CPU reset flag 15 1 read-only ALL_RESET_FLAG_CLR_PROCPU clear PRO CPU reset_flag 16 1 write-only ALL_RESET_FLAG_CLR_APPCPU clear APP CPU reset flag 17 1 write-only OCD_HALT_ON_RESET_APPCPU APPCPU OcdHaltOnReset 18 1 read-write OCD_HALT_ON_RESET_PROCPU PROCPU OcdHaltOnReset 19 1 read-write JTAG_RESET_FLAG_PROCPU configure jtag reset configure 20 1 read-only JTAG_RESET_FLAG_APPCPU configure jtag reset configure 21 1 read-only JTAG_RESET_FLAG_CLR_PROCPU configure jtag reset configure 22 1 write-only JTAG_RESET_FLAG_CLR_APPCPU configure jtag reset configure 23 1 write-only DRESET_MASK_APPCPU configure dreset configure 24 1 read-write DRESET_MASK_PROCPU configure dreset configure 25 1 read-write WAKEUP_STATE rtc configure register 0x3C 0x20 0x00060000 WAKEUP_ENA wakeup enable bitmap 15 17 read-write INT_ENA_RTC rtc configure register 0x40 0x20 SLP_WAKEUP_INT_ENA enable sleep wakeup interrupt 0 1 read-write SLP_REJECT_INT_ENA enable sleep reject interrupt 1 1 read-write WDT_INT_ENA enable RTC WDT interrupt 3 1 read-write BROWN_OUT_INT_ENA enable brown out interrupt 9 1 read-write MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 read-write SWD_INT_ENA enable super watch dog interrupt 15 1 read-write XTAL32K_DEAD_INT_ENA enable xtal32k_dead interrupt 16 1 read-write GLITCH_DET_INT_ENA enbale gitch det interrupt 19 1 read-write BBPLL_CAL_INT_ENA enbale bbpll cal end interrupt 20 1 read-write INT_RAW_RTC rtc configure register 0x44 0x20 SLP_WAKEUP_INT_RAW sleep wakeup interrupt raw 0 1 read-only SLP_REJECT_INT_RAW sleep reject interrupt raw 1 1 read-only WDT_INT_RAW RTC WDT interrupt raw 3 1 read-only BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-only MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-only SWD_INT_RAW super watch dog interrupt raw 15 1 read-only XTAL32K_DEAD_INT_RAW xtal32k dead detection interrupt raw 16 1 read-only GLITCH_DET_INT_RAW glitch_det_interrupt_raw 19 1 read-only BBPLL_CAL_INT_RAW bbpll cal end interrupt state 20 1 read-only INT_ST_RTC rtc configure register 0x48 0x20 SLP_WAKEUP_INT_ST sleep wakeup interrupt state 0 1 read-only SLP_REJECT_INT_ST sleep reject interrupt state 1 1 read-only WDT_INT_ST RTC WDT interrupt state 3 1 read-only BROWN_OUT_INT_ST brown out interrupt state 9 1 read-only MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-only SWD_INT_ST super watch dog interrupt state 15 1 read-only XTAL32K_DEAD_INT_ST xtal32k dead detection interrupt state 16 1 read-only GLITCH_DET_INT_ST glitch_det_interrupt state 19 1 read-only BBPLL_CAL_INT_ST bbpll cal end interrupt state 20 1 read-only INT_CLR_RTC rtc configure register 0x4C 0x20 SLP_WAKEUP_INT_CLR Clear sleep wakeup interrupt state 0 1 write-only SLP_REJECT_INT_CLR Clear sleep reject interrupt state 1 1 write-only WDT_INT_CLR Clear RTC WDT interrupt state 3 1 write-only BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 write-only MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 write-only SWD_INT_CLR Clear super watch dog interrupt state 15 1 write-only XTAL32K_DEAD_INT_CLR Clear RTC WDT interrupt state 16 1 write-only GLITCH_DET_INT_CLR Clear glitch det interrupt state 19 1 write-only BBPLL_CAL_INT_CLR clear bbpll cal end interrupt state 20 1 write-only STORE0 rtc configure register 0x50 0x20 SCRATCH0 reserved register 0 32 read-write STORE1 rtc configure register 0x54 0x20 SCRATCH1 reserved register 0 32 read-write STORE2 rtc configure register 0x58 0x20 SCRATCH2 reserved register 0 32 read-write STORE3 rtc configure register 0x5C 0x20 SCRATCH3 reserved register 0 32 read-write EXT_XTL_CONF rtc configure register 0x60 0x20 0x00066C80 XTAL32K_WDT_EN xtal 32k watch dog enable 0 1 read-write XTAL32K_WDT_CLK_FO xtal 32k watch dog clock force on 1 1 read-write XTAL32K_WDT_RESET xtal 32k watch dog sw reset 2 1 read-write XTAL32K_EXT_CLK_FO xtal 32k external xtal clock force on 3 1 read-write XTAL32K_AUTO_BACKUP xtal 32k switch to back up clock when xtal is dead 4 1 read-write XTAL32K_AUTO_RESTART xtal 32k restart xtal when xtal is dead 5 1 read-write XTAL32K_AUTO_RETURN xtal 32k switch back xtal when xtal is restarted 6 1 read-write XTAL32K_XPD_FORCE Xtal 32k xpd control by sw or fsm 7 1 read-write ENCKINIT_XTAL_32K apply an internal clock to help xtal 32k to start 8 1 read-write DBUF_XTAL_32K 0: single-end buffer 1: differential buffer 9 1 read-write DGM_XTAL_32K xtal_32k gm control 10 3 read-write DRES_XTAL_32K DRES_XTAL_32K 13 3 read-write XPD_XTAL_32K XPD_XTAL_32K 16 1 read-write DAC_XTAL_32K DAC_XTAL_32K 17 3 read-write WDT_STATE state of 32k_wdt 20 3 read-only XTAL32K_GPIO_SEL XTAL_32K sel. 0: external XTAL_32K 23 1 read-write XTL_EXT_CTR_LV 0: power down XTAL at high level 30 1 read-write XTL_EXT_CTR_EN enable gpio configure xtal power on 31 1 read-write EXT_WAKEUP_CONF rtc configure register 0x64 0x20 GPIO_WAKEUP_FILTER enable filter for gpio wakeup event 31 1 read-write SLP_REJECT_CONF rtc configure register 0x68 0x20 SLEEP_REJECT_ENA sleep reject enable 12 18 read-write LIGHT_SLP_REJECT_EN enable reject for light sleep 30 1 read-write DEEP_SLP_REJECT_EN enable reject for deep sleep 31 1 read-write CPU_PERIOD_CONF rtc configure register 0x6C 0x20 CPUSEL_CONF CPU sel option 29 1 read-write CPUPERIOD_SEL CPU clk sel option 30 2 read-write CLK_CONF rtc configure register 0x70 0x20 0x11583218 EFUSE_CLK_FORCE_GATING efuse_clk_force_gating 1 1 read-write EFUSE_CLK_FORCE_NOGATING efuse_clk_force_nogating 2 1 read-write CK8M_DIV_SEL_VLD used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel 3 1 read-write CK8M_DIV CK8M_D256_OUT divider. 00: div128 4 2 read-write ENB_CK8M disable CK8M and CK8M_D256_OUT 6 1 read-write ENB_CK8M_DIV 1: CK8M_D256_OUT is actually CK8M 7 1 read-write DIG_XTAL32K_EN enable CK_XTAL_32K for digital core (no relationship with RTC core) 8 1 read-write DIG_CLK8M_D256_EN enable CK8M_D256_OUT for digital core (no relationship with RTC core) 9 1 read-write DIG_CLK8M_EN enable CK8M for digital core (no relationship with RTC core) 10 1 read-write CK8M_DIV_SEL divider = reg_ck8m_div_sel + 1 12 3 read-write XTAL_FORCE_NOGATING XTAL force no gating during sleep 15 1 read-write CK8M_FORCE_NOGATING CK8M force no gating during sleep 16 1 read-write CK8M_DFREQ CK8M_DFREQ 17 8 read-write CK8M_FORCE_PD CK8M force power down 25 1 read-write CK8M_FORCE_PU CK8M force power up 26 1 read-write XTAL_GLOBAL_FORCE_GATING force enable xtal clk gating 27 1 read-write XTAL_GLOBAL_FORCE_NOGATING force bypass xtal clk gating 28 1 read-write FAST_CLK_RTC_SEL fast_clk_rtc sel. 0: XTAL div 4 29 1 read-write ANA_CLK_RTC_SEL slelect rtc slow clk 30 2 read-write SLOW_CLK_CONF rtc configure register 0x74 0x20 0x00400000 ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div 22 1 read-write ANA_CLK_DIV the clk divider num of RTC_CLK 23 8 read-write SLOW_CLK_NEXT_EDGE flag rtc_slow_clk_next_edge 31 1 read-write SDIO_CONF rtc configure register 0x78 0x20 0x0AB0BE0A SDIO_TIMER_TARGET timer count to apply reg_sdio_dcap after sdio power on 0 8 read-write SDIO_DTHDRV Tieh = 1 mode drive ability. Initially set to 0 to limit charge current 9 2 read-write SDIO_DCAP ability to prevent LDO from overshoot 11 2 read-write SDIO_INITI add resistor from ldo output to ground. 0: no res 13 2 read-write SDIO_EN_INITI 0 to set init[1:0]=0 15 1 read-write SDIO_DCURLIM tune current limit threshold when tieh = 0. About 800mA/(8+d) 16 3 read-write SDIO_MODECURLIM select current limit mode 19 1 read-write SDIO_ENCURLIM enable current limit 20 1 read-write SDIO_REG_PD_EN power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 21 1 read-write SDIO_FORCE 1: use SW option to control SDIO_REG 22 1 read-write SDIO_TIEH SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 23 1 read-write _1P8_READY read only register for REG1P8_READY 24 1 read-only DREFL_SDIO SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 25 2 read-write DREFM_SDIO SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 27 2 read-write DREFH_SDIO SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 29 2 read-write XPD_SDIO 31 1 read-write BIAS_CONF rtc configure register 0x7C 0x20 0x00010800 DG_VDD_DRV_B_SLP 0 8 read-write DG_VDD_DRV_B_SLP_EN 8 1 read-write BIAS_BUF_IDLE bias buf when rtc in normal work state 10 1 read-write BIAS_BUF_WAKE bias buf when rtc in wakeup state 11 1 read-write BIAS_BUF_DEEP_SLP bias buf when rtc in sleep state 12 1 read-write BIAS_BUF_MONITOR bias buf when rtc in monitor state 13 1 read-write PD_CUR_DEEP_SLP xpd cur when rtc in sleep_state 14 1 read-write PD_CUR_MONITOR xpd cur when rtc in monitor state 15 1 read-write BIAS_SLEEP_DEEP_SLP bias_sleep when rtc in sleep_state 16 1 read-write BIAS_SLEEP_MONITOR bias_sleep when rtc in monitor state 17 1 read-write DBG_ATTEN_DEEP_SLP DBG_ATTEN when rtc in sleep state 18 4 read-write DBG_ATTEN_MONITOR DBG_ATTEN when rtc in monitor state 22 4 read-write RTC_CNTL rtc configure register 0x80 0x20 0xA0000000 DIG_REG_CAL_EN software enable digital regulator cali 7 1 read-write SCK_DCAP SCK_DCAP 14 8 read-write DBOOST_FORCE_PD RTC_DBOOST force power down 28 1 read-write DBOOST_FORCE_PU RTC_DBOOST force power up 29 1 read-write REGULATOR_FORCE_PD RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) 30 1 read-write REGULATOR_FORCE_PU RTC_REG force power up 31 1 read-write PWC rtc configure register 0x84 0x20 PAD_FORCE_HOLD rtc pad force hold 21 1 read-write DIG_PWC rtc configure register 0x88 0x20 0x00555010 VDD_SPI_PWR_DRV vdd_spi drv's software value 0 2 read-write VDD_SPI_PWR_FORCE vdd_spi drv use software value 2 1 read-write LSLP_MEM_FORCE_PD memories in digital core force PD in sleep 3 1 read-write LSLP_MEM_FORCE_PU memories in digital core force PU in sleep 4 1 read-write BT_FORCE_PD bt force power down 11 1 read-write BT_FORCE_PU bt force power up 12 1 read-write DG_PERI_FORCE_PD digital peri force power down 13 1 read-write DG_PERI_FORCE_PU digital peri force power up 14 1 read-write FASTMEM_FORCE_LPD fastmemory retention mode in sleep 15 1 read-write FASTMEM_FORCE_LPU fastmemory donlt entry retention mode in sleep 16 1 read-write WIFI_FORCE_PD wifi force power down 17 1 read-write WIFI_FORCE_PU wifi force power up 18 1 read-write DG_WRAP_FORCE_PD digital core force power down 19 1 read-write DG_WRAP_FORCE_PU digital core force power up 20 1 read-write CPU_TOP_FORCE_PD cpu core force power down 21 1 read-write CPU_TOP_FORCE_PU cpu force power up 22 1 read-write BT_PD_EN enable power down bt in sleep 27 1 read-write DG_PERI_PD_EN enable power down digital peri in sleep 28 1 read-write CPU_TOP_PD_EN enable power down cpu in sleep 29 1 read-write WIFI_PD_EN enable power down wifi in sleep 30 1 read-write DG_WRAP_PD_EN enable power down digital wrap in sleep 31 1 read-write DIG_ISO rtc configure register 0x8C 0x20 0xAA805080 FORCE_OFF DIG_ISO force off 7 1 read-write FORCE_ON DIG_ISO force on 8 1 read-write DG_PAD_AUTOHOLD read only register to indicate digital pad auto-hold status 9 1 read-only CLR_DG_PAD_AUTOHOLD wtite only register to clear digital pad auto-hold 10 1 write-only DG_PAD_AUTOHOLD_EN digital pad enable auto-hold 11 1 read-write DG_PAD_FORCE_NOISO digital pad force no ISO 12 1 read-write DG_PAD_FORCE_ISO digital pad force ISO 13 1 read-write DG_PAD_FORCE_UNHOLD digital pad force un-hold 14 1 read-write DG_PAD_FORCE_HOLD digital pad force hold 15 1 read-write BT_FORCE_ISO bt force ISO 22 1 read-write BT_FORCE_NOISO bt force no ISO 23 1 read-write DG_PERI_FORCE_ISO Digital peri force ISO 24 1 read-write DG_PERI_FORCE_NOISO digital peri force no ISO 25 1 read-write CPU_TOP_FORCE_ISO cpu force ISO 26 1 read-write CPU_TOP_FORCE_NOISO cpu force no ISO 27 1 read-write WIFI_FORCE_ISO wifi force ISO 28 1 read-write WIFI_FORCE_NOISO wifi force no ISO 29 1 read-write DG_WRAP_FORCE_ISO digital core force ISO 30 1 read-write DG_WRAP_FORCE_NOISO digital core force no ISO 31 1 read-write WDTCONFIG0 rtc configure register 0x90 0x20 0x00013214 WDT_CHIP_RESET_WIDTH chip reset siginal pulse width 0 8 read-write WDT_CHIP_RESET_EN wdt reset whole chip enable 8 1 read-write WDT_PAUSE_IN_SLP pause WDT in sleep 9 1 read-write WDT_APPCPU_RESET_EN enable WDT reset APP CPU 10 1 read-write WDT_PROCPU_RESET_EN enable WDT reset PRO CPU 11 1 read-write WDT_FLASHBOOT_MOD_EN enable WDT in flash boot 12 1 read-write WDT_SYS_RESET_LENGTH system reset counter length 13 3 read-write WDT_CPU_RESET_LENGTH CPU reset counter length 16 3 read-write WDT_STG3 1: interrupt stage en 19 3 read-write WDT_STG2 1: interrupt stage en 22 3 read-write WDT_STG1 1: interrupt stage en 25 3 read-write WDT_STG0 1: interrupt stage en 28 3 read-write WDT_EN enable rtc wdt 31 1 read-write WDTCONFIG1 rtc configure register 0x94 0x20 0x00030D40 WDT_STG0_HOLD the hold time of stage0 0 32 read-write WDTCONFIG2 rtc configure register 0x98 0x20 0x00013880 WDT_STG1_HOLD the hold time of stage1 0 32 read-write WDTCONFIG3 rtc configure register 0x9C 0x20 0x00000FFF WDT_STG2_HOLD the hold time of stage2 0 32 read-write WDTCONFIG4 rtc configure register 0xA0 0x20 0x00000FFF WDT_STG3_HOLD the hold time of stage3 0 32 read-write WDTFEED rtc configure register 0xA4 0x20 WDT_FEED sw feed rtc wdt 31 1 write-only WDTWPROTECT rtc configure register 0xA8 0x20 WDT_WKEY the key of rtc wdt 0 32 read-write SWD_CONF rtc configure register 0xAC 0x20 0x04B00000 SWD_RESET_FLAG swd reset flag 0 1 read-only SWD_FEED_INT swd interrupt for feeding 1 1 read-only SWD_BYPASS_RST Bypass swd rst 17 1 read-write SWD_SIGNAL_WIDTH adjust signal width send to swd 18 10 read-write SWD_RST_FLAG_CLR reset swd reset flag 28 1 write-only SWD_FEED Sw feed swd 29 1 write-only SWD_DISABLE disabel SWD 30 1 read-write SWD_AUTO_FEED_EN automatically feed swd when int comes 31 1 read-write SWD_WPROTECT rtc configure register 0xB0 0x20 SWD_WKEY the key of super wdt 0 32 read-write SW_CPU_STALL rtc configure register 0xB4 0x20 SW_STALL_APPCPU_C1 {reg_sw_stall_appcpu_c1[5:0] 20 6 read-write SW_STALL_PROCPU_C1 stall cpu by software 26 6 read-write STORE4 rtc configure register 0xB8 0x20 SCRATCH4 reserved register 0 32 read-write STORE5 rtc configure register 0xBC 0x20 SCRATCH5 reserved register 0 32 read-write STORE6 rtc configure register 0xC0 0x20 SCRATCH6 reserved register 0 32 read-write STORE7 rtc configure register 0xC4 0x20 SCRATCH7 reserved register 0 32 read-write LOW_POWER_ST rtc configure register 0xC8 0x20 XPD_ROM0 rom0 power down 0 1 read-only XPD_DIG_DCDC External DCDC power down 2 1 read-only PERI_ISO rtc peripheral iso 3 1 read-only XPD_RTC_PERI rtc peripheral power down 4 1 read-only WIFI_ISO wifi iso 5 1 read-only XPD_WIFI wifi wrap power down 6 1 read-only DIG_ISO digital wrap iso 7 1 read-only XPD_DIG digital wrap power down 8 1 read-only TOUCH_STATE_START touch should start to work 9 1 read-only TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-only TOUCH_STATE_SLP touch is in sleep state 11 1 read-only TOUCH_STATE_DONE touch is done 12 1 read-only COCPU_STATE_START ulp/cocpu should start to work 13 1 read-only COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-only COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-only COCPU_STATE_DONE ulp/cocpu is done 16 1 read-only MAIN_STATE_XTAL_ISO no use any more 17 1 read-only MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-only RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-only MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-only IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-only IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-only MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-only MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-only MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-only MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-only MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-only MAIN_STATE rtc main state machine status 28 4 read-only DIAG0 rtc configure register 0xCC 0x20 LOW_POWER_DIAG1 0 32 read-only PAD_HOLD rtc configure register 0xD0 0x20 GPIO_PIN0_HOLD the hold configure of rtc gpio0 0 1 read-write GPIO_PIN1_HOLD the hold configure of rtc gpio1 1 1 read-write GPIO_PIN2_HOLD the hold configure of rtc gpio2 2 1 read-write GPIO_PIN3_HOLD the hold configure of rtc gpio3 3 1 read-write GPIO_PIN4_HOLD the hold configure of rtc gpio4 4 1 read-write GPIO_PIN5_HOLD the hold configure of rtc gpio5 5 1 read-write DIG_PAD_HOLD rtc configure register 0xD4 0x20 DIG_PAD_HOLD the configure of digital pad 0 32 read-write BROWN_OUT rtc configure register 0xD8 0x20 0x43FF0010 BROWN_OUT_INT_WAIT brown out interrupt wait cycles 4 10 read-write BROWN_OUT_CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write BROWN_OUT_PD_RF_ENA enable power down RF when brown out happens 15 1 read-write BROWN_OUT_RST_WAIT brown out reset wait cycles 16 10 read-write BROWN_OUT_RST_ENA enable brown out reset 26 1 read-write BROWN_OUT_RST_SEL 1: 4-pos reset 27 1 read-write BROWN_OUT_ANA_RST_EN brown_out origin reset enable 28 1 read-write BROWN_OUT_CNT_CLR clear brown out counter 29 1 write-only BROWN_OUT_ENA enable brown out 30 1 read-write DET the flag of brown det from analog 31 1 read-only TIME_LOW1 rtc configure register 0xDC 0x20 TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 read-only TIME_HIGH1 rtc configure register 0xE0 0x20 TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 read-only XTAL32K_CLK_FACTOR rtc configure register 0xE4 0x20 XTAL32K_CLK_FACTOR xtal 32k watch dog backup clock factor 0 32 read-write XTAL32K_CONF rtc configure register 0xE8 0x20 0x0FF00000 XTAL32K_RETURN_WAIT cycles to wait to return noral xtal 32k 0 4 read-write XTAL32K_RESTART_WAIT cycles to wait to repower on xtal 32k 4 16 read-write XTAL32K_WDT_TIMEOUT If no clock detected for this amount of time 20 8 read-write XTAL32K_STABLE_THRES if restarted xtal32k period is smaller than this 28 4 read-write USB_CONF rtc configure register 0xEC 0x20 IO_MUX_RESET_DISABLE disable io_mux reset 18 1 read-write SLP_REJECT_CAUSE RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG 0xF0 0x20 REJECT_CAUSE sleep reject cause 0 18 read-only OPTION1 rtc configure register 0xF4 0x20 FORCE_DOWNLOAD_BOOT force chip entry download mode 0 1 read-write SLP_WAKEUP_CAUSE RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG 0xF8 0x20 WAKEUP_CAUSE sleep wakeup cause 0 17 read-only ULP_CP_TIMER_1 rtc configure register 0xFC 0x20 0x0000C800 ULP_CP_TIMER_SLP_CYCLE sleep cycles for ULP-coprocessor timer 8 24 read-write INT_ENA_RTC_W1TS rtc configure register 0x100 0x20 SLP_WAKEUP_INT_ENA_W1TS enable sleep wakeup interrupt 0 1 write-only SLP_REJECT_INT_ENA_W1TS enable sleep reject interrupt 1 1 write-only WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 write-only BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 write-only MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 write-only SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 write-only XTAL32K_DEAD_INT_ENA_W1TS enable xtal32k_dead interrupt 16 1 write-only GLITCH_DET_INT_ENA_W1TS enbale gitch det interrupt 19 1 write-only BBPLL_CAL_INT_ENA_W1TS enbale bbpll cal interrupt 20 1 write-only INT_ENA_RTC_W1TC rtc configure register 0x104 0x20 SLP_WAKEUP_INT_ENA_W1TC clear sleep wakeup interrupt enable 0 1 write-only SLP_REJECT_INT_ENA_W1TC clear sleep reject interrupt enable 1 1 write-only WDT_INT_ENA_W1TC clear RTC WDT interrupt enable 3 1 write-only BROWN_OUT_INT_ENA_W1TC clear brown out interrupt enable 9 1 write-only MAIN_TIMER_INT_ENA_W1TC Clear RTC main timer interrupt enable 10 1 write-only SWD_INT_ENA_W1TC clear super watch dog interrupt enable 15 1 write-only XTAL32K_DEAD_INT_ENA_W1TC clear xtal32k_dead interrupt enable 16 1 write-only GLITCH_DET_INT_ENA_W1TC clear gitch det interrupt enable 19 1 write-only BBPLL_CAL_INT_ENA_W1TC clear bbpll cal interrupt enable 20 1 write-only RETENTION_CTRL rtc configure register 0x108 0x20 0xA0D00000 RETENTION_CLK_SEL Retention clk sel 18 1 read-write RETENTION_DONE_WAIT Retention done wait time 19 3 read-write RETENTION_CLKOFF_WAIT Retention clkoff wait time 22 4 read-write RETENTION_EN enable cpu retention when light sleep 26 1 read-write RETENTION_WAIT wait cycles for rention operation 27 5 read-write FIB_SEL rtc configure register 0x10C 0x20 0x00000007 FIB_SEL select use analog fib signal 0 3 read-write GPIO_WAKEUP rtc configure register 0x110 0x20 GPIO_WAKEUP_STATUS rtc gpio wakeup flag 0 6 read-only GPIO_WAKEUP_STATUS_CLR clear rtc gpio wakeup flag 6 1 read-write GPIO_PIN_CLK_GATE enable rtc io clk gate 7 1 read-write GPIO_PIN5_INT_TYPE configure gpio wakeup type 8 3 read-write GPIO_PIN4_INT_TYPE configure gpio wakeup type 11 3 read-write GPIO_PIN3_INT_TYPE configure gpio wakeup type 14 3 read-write GPIO_PIN2_INT_TYPE configure gpio wakeup type 17 3 read-write GPIO_PIN1_INT_TYPE configure gpio wakeup type 20 3 read-write GPIO_PIN0_INT_TYPE configure gpio wakeup type 23 3 read-write GPIO_PIN5_WAKEUP_ENABLE enable wakeup from rtc gpio5 26 1 read-write GPIO_PIN4_WAKEUP_ENABLE enable wakeup from rtc gpio4 27 1 read-write GPIO_PIN3_WAKEUP_ENABLE enable wakeup from rtc gpio3 28 1 read-write GPIO_PIN2_WAKEUP_ENABLE enable wakeup from rtc gpio2 29 1 read-write GPIO_PIN1_WAKEUP_ENABLE enable wakeup from rtc gpio1 30 1 read-write GPIO_PIN0_WAKEUP_ENABLE enable wakeup from rtc gpio0 31 1 read-write DBG_SEL rtc configure register 0x114 0x20 DEBUG_12M_NO_GATING use for debug 1 1 read-write DEBUG_BIT_SEL use for debug 2 5 read-write DEBUG_SEL0 use for debug 7 5 read-write DEBUG_SEL1 use for debug 12 5 read-write DEBUG_SEL2 use for debug 17 5 read-write DEBUG_SEL3 use for debug 22 5 read-write DEBUG_SEL4 use for debug 27 5 read-write DBG_MAP rtc configure register 0x118 0x20 GPIO_PIN5_MUX_SEL use for debug 2 1 read-write GPIO_PIN4_MUX_SEL use for debug 3 1 read-write GPIO_PIN3_MUX_SEL use for debug 4 1 read-write GPIO_PIN2_MUX_SEL use for debug 5 1 read-write GPIO_PIN1_MUX_SEL use for debug 6 1 read-write GPIO_PIN0_MUX_SEL use for debug 7 1 read-write GPIO_PIN5_FUN_SEL use for debug 8 4 read-write GPIO_PIN4_FUN_SEL use for debug 12 4 read-write GPIO_PIN3_FUN_SEL use for debug 16 4 read-write GPIO_PIN2_FUN_SEL use for debug 20 4 read-write GPIO_PIN1_FUN_SEL use for debug 24 4 read-write GPIO_PIN0_FUN_SEL use for debug 28 4 read-write SENSOR_CTRL rtc configure register 0x11C 0x20 SAR2_PWDET_CCT reg_sar2_pwdet_cct 27 3 read-write FORCE_XPD_SAR force power up SAR 30 2 read-write DBG_SAR_SEL rtc configure register 0x120 0x20 SAR_DEBUG_SEL use for debug 27 5 read-write PG_CTRL rtc configure register 0x124 0x20 POWER_GLITCH_DSENSE power glitch desense 26 2 read-write POWER_GLITCH_FORCE_PD force disable power glitch 28 1 read-write POWER_GLITCH_FORCE_PU force enable power glitch 29 1 read-write POWER_GLITCH_EFUSE_SEL use efuse value control power glitch enable 30 1 read-write POWER_GLITCH_EN enable power glitch 31 1 read-write DATE rtc configure register 0x1FC 0x20 0x02007270 DATE verision 0 28 read-write SENSITIVE Sensitive SENSITIVE 0x600C1000 0x0 0x178 registers ROM_TABLE_LOCK SENSITIVE_ROM_TABLE_LOCK_REG 0x0 0x20 ROM_TABLE_LOCK rom_table_lock 0 1 read-write ROM_TABLE SENSITIVE_ROM_TABLE_REG 0x4 0x20 ROM_TABLE rom_table 0 32 read-write PRIVILEGE_MODE_SEL_LOCK SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG 0x8 0x20 PRIVILEGE_MODE_SEL_LOCK privilege_mode_sel_lock 0 1 read-write PRIVILEGE_MODE_SEL SENSITIVE_PRIVILEGE_MODE_SEL_REG 0xC 0x20 PRIVILEGE_MODE_SEL privilege_mode_sel 0 1 read-write APB_PERIPHERAL_ACCESS_0 SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG 0x10 0x20 APB_PERIPHERAL_ACCESS_LOCK apb_peripheral_access_lock 0 1 read-write APB_PERIPHERAL_ACCESS_1 SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG 0x14 0x20 0x00000001 APB_PERIPHERAL_ACCESS_SPLIT_BURST apb_peripheral_access_split_burst 0 1 read-write INTERNAL_SRAM_USAGE_0 SENSITIVE_INTERNAL_SRAM_USAGE_0_REG 0x18 0x20 INTERNAL_SRAM_USAGE_LOCK internal_sram_usage_lock 0 1 read-write INTERNAL_SRAM_USAGE_1 SENSITIVE_INTERNAL_SRAM_USAGE_1_REG 0x1C 0x20 0x0000000F INTERNAL_SRAM_USAGE_CPU_CACHE internal_sram_usage_cpu_cache 0 1 read-write INTERNAL_SRAM_USAGE_CPU_SRAM internal_sram_usage_cpu_sram 1 3 read-write INTERNAL_SRAM_USAGE_3 SENSITIVE_INTERNAL_SRAM_USAGE_3_REG 0x20 0x20 INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM internal_sram_usage_mac_dump_sram 0 3 read-write INTERNAL_SRAM_ALLOC_MAC_DUMP internal_sram_alloc_mac_dump 3 1 read-write INTERNAL_SRAM_USAGE_4 SENSITIVE_INTERNAL_SRAM_USAGE_4_REG 0x24 0x20 INTERNAL_SRAM_USAGE_LOG_SRAM internal_sram_usage_log_sram 0 1 read-write CACHE_TAG_ACCESS_0 SENSITIVE_CACHE_TAG_ACCESS_0_REG 0x28 0x20 CACHE_TAG_ACCESS_LOCK cache_tag_access_lock 0 1 read-write CACHE_TAG_ACCESS_1 SENSITIVE_CACHE_TAG_ACCESS_1_REG 0x2C 0x20 0x0000000F PRO_I_TAG_RD_ACS pro_i_tag_rd_acs 0 1 read-write PRO_I_TAG_WR_ACS pro_i_tag_wr_acs 1 1 read-write PRO_D_TAG_RD_ACS pro_d_tag_rd_acs 2 1 read-write PRO_D_TAG_WR_ACS pro_d_tag_wr_acs 3 1 read-write CACHE_MMU_ACCESS_0 SENSITIVE_CACHE_MMU_ACCESS_0_REG 0x30 0x20 CACHE_MMU_ACCESS_LOCK cache_mmu_access_lock 0 1 read-write CACHE_MMU_ACCESS_1 SENSITIVE_CACHE_MMU_ACCESS_1_REG 0x34 0x20 0x00000003 PRO_MMU_RD_ACS pro_mmu_rd_acs 0 1 read-write PRO_MMU_WR_ACS pro_mmu_wr_acs 1 1 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG 0x38 0x20 DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK dma_apbperi_spi2_pms_constrain_lock 0 1 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG 0x3C 0x20 0x000FF0FF DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG 0x40 0x20 DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK dma_apbperi_uchi0_pms_constrain_lock 0 1 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG 0x44 0x20 0x000FF0FF DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG 0x48 0x20 DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK dma_apbperi_i2s0_pms_constrain_lock 0 1 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG 0x4C 0x20 0x000FF0FF DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG 0x50 0x20 DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK dma_apbperi_mac_pms_constrain_lock 0 1 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG 0x54 0x20 0x000FF0FF DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_mac_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_mac_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_mac_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_mac_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_mac_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_mac_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_mac_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_mac_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG 0x58 0x20 DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK dma_apbperi_backup_pms_constrain_lock 0 1 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG 0x5C 0x20 0x000FF0FF DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_backup_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_backup_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_backup_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_backup_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_backup_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_backup_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_backup_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_backup_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG 0x60 0x20 DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK dma_apbperi_lc_pms_constrain_lock 0 1 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG 0x64 0x20 0x000FF0FF DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_lc_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_lc_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_lc_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_lc_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_lc_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_lc_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_lc_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_lc_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG 0x68 0x20 DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK dma_apbperi_aes_pms_constrain_lock 0 1 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG 0x6C 0x20 0x000FF0FF DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_aes_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_aes_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_aes_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_aes_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_aes_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_aes_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_aes_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_aes_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG 0x70 0x20 DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK dma_apbperi_sha_pms_constrain_lock 0 1 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG 0x74 0x20 0x000FF0FF DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_sha_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_sha_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_sha_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_sha_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_sha_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_sha_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_sha_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_sha_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG 0x78 0x20 DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK dma_apbperi_adc_dac_pms_constrain_lock 0 1 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG 0x7C 0x20 0x000FF0FF DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0 0 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1 2 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2 4 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3 6 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0 12 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1 14 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2 16 2 read-write DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3 18 2 read-write DMA_APBPERI_PMS_MONITOR_0 SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG 0x80 0x20 DMA_APBPERI_PMS_MONITOR_LOCK dma_apbperi_pms_monitor_lock 0 1 read-write DMA_APBPERI_PMS_MONITOR_1 SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG 0x84 0x20 0x00000003 DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR dma_apbperi_pms_monitor_violate_clr 0 1 read-write DMA_APBPERI_PMS_MONITOR_VIOLATE_EN dma_apbperi_pms_monitor_violate_en 1 1 read-write DMA_APBPERI_PMS_MONITOR_2 SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG 0x88 0x20 DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR dma_apbperi_pms_monitor_violate_intr 0 1 read-only DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD dma_apbperi_pms_monitor_violate_status_world 1 2 read-only DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR dma_apbperi_pms_monitor_violate_status_addr 3 24 read-only DMA_APBPERI_PMS_MONITOR_3 SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG 0x8C 0x20 DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR dma_apbperi_pms_monitor_violate_status_wr 0 1 read-only DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN dma_apbperi_pms_monitor_violate_status_byteen 1 4 read-only CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG 0x90 0x20 CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK core_x_iram0_dram0_dma_split_line_constrain_lock 0 1 read-write CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG 0x94 0x20 CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 core_x_iram0_dram0_dma_sram_category_0 0 2 read-write CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 core_x_iram0_dram0_dma_sram_category_1 2 2 read-write CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 core_x_iram0_dram0_dma_sram_category_2 4 2 read-write CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR core_x_iram0_dram0_dma_sram_splitaddr 14 8 read-write CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG 0x98 0x20 CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 core_x_iram0_sram_line_0_category_0 0 2 read-write CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 core_x_iram0_sram_line_0_category_1 2 2 read-write CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 core_x_iram0_sram_line_0_category_2 4 2 read-write CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR core_x_iram0_sram_line_0_splitaddr 14 8 read-write CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG 0x9C 0x20 CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 core_x_iram0_sram_line_1_category_0 0 2 read-write CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 core_x_iram0_sram_line_1_category_1 2 2 read-write CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 core_x_iram0_sram_line_1_category_2 4 2 read-write CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR core_x_iram0_sram_line_1_splitaddr 14 8 read-write CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG 0xA0 0x20 CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 core_x_dram0_dma_sram_line_0_category_0 0 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 core_x_dram0_dma_sram_line_0_category_1 2 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 core_x_dram0_dma_sram_line_0_category_2 4 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR core_x_dram0_dma_sram_line_0_splitaddr 14 8 read-write CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG 0xA4 0x20 CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 core_x_dram0_dma_sram_line_1_category_0 0 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 core_x_dram0_dma_sram_line_1_category_1 2 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 core_x_dram0_dma_sram_line_1_category_2 4 2 read-write CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR core_x_dram0_dma_sram_line_1_splitaddr 14 8 read-write CORE_X_IRAM0_PMS_CONSTRAIN_0 SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG 0xA8 0x20 CORE_X_IRAM0_PMS_CONSTRAIN_LOCK core_x_iram0_pms_constrain_lock 0 1 read-write CORE_X_IRAM0_PMS_CONSTRAIN_1 SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG 0xAC 0x20 0x001C7FFF CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 core_x_iram0_pms_constrain_sram_world_1_pms_0 0 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 core_x_iram0_pms_constrain_sram_world_1_pms_1 3 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 core_x_iram0_pms_constrain_sram_world_1_pms_2 6 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 core_x_iram0_pms_constrain_sram_world_1_pms_3 9 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0 12 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS core_x_iram0_pms_constrain_rom_world_1_pms 18 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_2 SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG 0xB0 0x20 0x001C7FFF CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 core_x_iram0_pms_constrain_sram_world_0_pms_0 0 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 core_x_iram0_pms_constrain_sram_world_0_pms_1 3 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 core_x_iram0_pms_constrain_sram_world_0_pms_2 6 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 core_x_iram0_pms_constrain_sram_world_0_pms_3 9 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0 12 3 read-write CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS core_x_iram0_pms_constrain_rom_world_0_pms 18 3 read-write CORE_0_IRAM0_PMS_MONITOR_0 SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG 0xB4 0x20 CORE_0_IRAM0_PMS_MONITOR_LOCK core_0_iram0_pms_monitor_lock 0 1 read-write CORE_0_IRAM0_PMS_MONITOR_1 SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG 0xB8 0x20 0x00000003 CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR core_0_iram0_pms_monitor_violate_clr 0 1 read-write CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN core_0_iram0_pms_monitor_violate_en 1 1 read-write CORE_0_IRAM0_PMS_MONITOR_2 SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG 0xBC 0x20 CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR core_0_iram0_pms_monitor_violate_intr 0 1 read-only CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR core_0_iram0_pms_monitor_violate_status_wr 1 1 read-only CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE core_0_iram0_pms_monitor_violate_status_loadstore 2 1 read-only CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD core_0_iram0_pms_monitor_violate_status_world 3 2 read-only CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR core_0_iram0_pms_monitor_violate_status_addr 5 24 read-only CORE_X_DRAM0_PMS_CONSTRAIN_0 SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG 0xC0 0x20 CORE_X_DRAM0_PMS_CONSTRAIN_LOCK core_x_dram0_pms_constrain_lock 0 1 read-write CORE_X_DRAM0_PMS_CONSTRAIN_1 SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG 0xC4 0x20 0x0F0FF0FF CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 core_x_dram0_pms_constrain_sram_world_0_pms_0 0 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 core_x_dram0_pms_constrain_sram_world_0_pms_1 2 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 core_x_dram0_pms_constrain_sram_world_0_pms_2 4 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 core_x_dram0_pms_constrain_sram_world_0_pms_3 6 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 core_x_dram0_pms_constrain_sram_world_1_pms_0 12 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 core_x_dram0_pms_constrain_sram_world_1_pms_1 14 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 core_x_dram0_pms_constrain_sram_world_1_pms_2 16 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 core_x_dram0_pms_constrain_sram_world_1_pms_3 18 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS core_x_dram0_pms_constrain_rom_world_0_pms 24 2 read-write CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS core_x_dram0_pms_constrain_rom_world_1_pms 26 2 read-write CORE_0_DRAM0_PMS_MONITOR_0 SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG 0xC8 0x20 CORE_0_DRAM0_PMS_MONITOR_LOCK core_0_dram0_pms_monitor_lock 0 1 read-write CORE_0_DRAM0_PMS_MONITOR_1 SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG 0xCC 0x20 0x00000003 CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR core_0_dram0_pms_monitor_violate_clr 0 1 read-write CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN core_0_dram0_pms_monitor_violate_en 1 1 read-write CORE_0_DRAM0_PMS_MONITOR_2 SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG 0xD0 0x20 CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR core_0_dram0_pms_monitor_violate_intr 0 1 read-only CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK core_0_dram0_pms_monitor_violate_status_lock 1 1 read-only CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD core_0_dram0_pms_monitor_violate_status_world 2 2 read-only CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR core_0_dram0_pms_monitor_violate_status_addr 4 24 read-only CORE_0_DRAM0_PMS_MONITOR_3 SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG 0xD4 0x20 CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR core_0_dram0_pms_monitor_violate_status_wr 0 1 read-only CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN core_0_dram0_pms_monitor_violate_status_byteen 1 4 read-only CORE_0_PIF_PMS_CONSTRAIN_0 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG 0xD8 0x20 CORE_0_PIF_PMS_CONSTRAIN_LOCK core_0_pif_pms_constrain_lock 0 1 read-write CORE_0_PIF_PMS_CONSTRAIN_1 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG 0xDC 0x20 0xCF0FFFFF CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART core_0_pif_pms_constrain_world_0_uart 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 core_0_pif_pms_constrain_world_0_g0spi_1 2 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 core_0_pif_pms_constrain_world_0_g0spi_0 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO core_0_pif_pms_constrain_world_0_gpio 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 core_0_pif_pms_constrain_world_0_fe2 8 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE core_0_pif_pms_constrain_world_0_fe 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER core_0_pif_pms_constrain_world_0_timer 12 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC core_0_pif_pms_constrain_world_0_rtc 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX core_0_pif_pms_constrain_world_0_io_mux 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG core_0_pif_pms_constrain_world_0_wdg 18 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC core_0_pif_pms_constrain_world_0_misc 24 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C core_0_pif_pms_constrain_world_0_i2c 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 core_0_pif_pms_constrain_world_0_uart1 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_2 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG 0xE0 0x20 0xFCC30CF3 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT core_0_pif_pms_constrain_world_0_bt 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 core_0_pif_pms_constrain_world_0_i2c_ext0 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 core_0_pif_pms_constrain_world_0_uhci0 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT core_0_pif_pms_constrain_world_0_rmt 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC core_0_pif_pms_constrain_world_0_ledc 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB core_0_pif_pms_constrain_world_0_bb 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP core_0_pif_pms_constrain_world_0_timergroup 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 core_0_pif_pms_constrain_world_0_timergroup1 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER core_0_pif_pms_constrain_world_0_systimer 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_3 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG 0xE4 0x20 0x3CC0CC33 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 core_0_pif_pms_constrain_world_0_spi_2 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL core_0_pif_pms_constrain_world_0_apb_ctrl 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN core_0_pif_pms_constrain_world_0_can 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 core_0_pif_pms_constrain_world_0_i2s1 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT core_0_pif_pms_constrain_world_0_rwbt 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC core_0_pif_pms_constrain_world_0_wifimac 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR core_0_pif_pms_constrain_world_0_pwr 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_4 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG 0xE8 0x20 0xFFFFF3FC CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP core_0_pif_pms_constrain_world_0_usb_wrap 2 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI core_0_pif_pms_constrain_world_0_crypto_peri 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA core_0_pif_pms_constrain_world_0_crypto_dma 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC core_0_pif_pms_constrain_world_0_apb_adc 8 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR core_0_pif_pms_constrain_world_0_bt_pwr 12 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE core_0_pif_pms_constrain_world_0_usb_device 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM core_0_pif_pms_constrain_world_0_system 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE core_0_pif_pms_constrain_world_0_sensitive 18 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT core_0_pif_pms_constrain_world_0_interrupt 20 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY core_0_pif_pms_constrain_world_0_dma_copy 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG core_0_pif_pms_constrain_world_0_cache_config 24 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD core_0_pif_pms_constrain_world_0_ad 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO core_0_pif_pms_constrain_world_0_dio 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER core_0_pif_pms_constrain_world_0_world_controller 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_5 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG 0xEC 0x20 0xCF0FFFFF CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART core_0_pif_pms_constrain_world_1_uart 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 core_0_pif_pms_constrain_world_1_g0spi_1 2 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 core_0_pif_pms_constrain_world_1_g0spi_0 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO core_0_pif_pms_constrain_world_1_gpio 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 core_0_pif_pms_constrain_world_1_fe2 8 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE core_0_pif_pms_constrain_world_1_fe 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER core_0_pif_pms_constrain_world_1_timer 12 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC core_0_pif_pms_constrain_world_1_rtc 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX core_0_pif_pms_constrain_world_1_io_mux 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG core_0_pif_pms_constrain_world_1_wdg 18 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC core_0_pif_pms_constrain_world_1_misc 24 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C core_0_pif_pms_constrain_world_1_i2c 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 core_0_pif_pms_constrain_world_1_uart1 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_6 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG 0xF0 0x20 0xFCC30CF3 CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT core_0_pif_pms_constrain_world_1_bt 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 core_0_pif_pms_constrain_world_1_i2c_ext0 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 core_0_pif_pms_constrain_world_1_uhci0 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT core_0_pif_pms_constrain_world_1_rmt 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC core_0_pif_pms_constrain_world_1_ledc 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB core_0_pif_pms_constrain_world_1_bb 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP core_0_pif_pms_constrain_world_1_timergroup 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 core_0_pif_pms_constrain_world_1_timergroup1 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER core_0_pif_pms_constrain_world_1_systimer 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_7 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG 0xF4 0x20 0x3CC0CC33 CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 core_0_pif_pms_constrain_world_1_spi_2 0 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL core_0_pif_pms_constrain_world_1_apb_ctrl 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN core_0_pif_pms_constrain_world_1_can 10 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 core_0_pif_pms_constrain_world_1_i2s1 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT core_0_pif_pms_constrain_world_1_rwbt 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC core_0_pif_pms_constrain_world_1_wifimac 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR core_0_pif_pms_constrain_world_1_pwr 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_8 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG 0xF8 0x20 0xFFFFF3FC CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP core_0_pif_pms_constrain_world_1_usb_wrap 2 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI core_0_pif_pms_constrain_world_1_crypto_peri 4 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA core_0_pif_pms_constrain_world_1_crypto_dma 6 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC core_0_pif_pms_constrain_world_1_apb_adc 8 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR core_0_pif_pms_constrain_world_1_bt_pwr 12 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE core_0_pif_pms_constrain_world_1_usb_device 14 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM core_0_pif_pms_constrain_world_1_system 16 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE core_0_pif_pms_constrain_world_1_sensitive 18 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT core_0_pif_pms_constrain_world_1_interrupt 20 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY core_0_pif_pms_constrain_world_1_dma_copy 22 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG core_0_pif_pms_constrain_world_1_cache_config 24 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD core_0_pif_pms_constrain_world_1_ad 26 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO core_0_pif_pms_constrain_world_1_dio 28 2 read-write CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER core_0_pif_pms_constrain_world_1_world_controller 30 2 read-write CORE_0_PIF_PMS_CONSTRAIN_9 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG 0xFC 0x20 0x003FFFFF CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 core_0_pif_pms_constrain_rtcfast_spltaddr_world_0 0 11 read-write CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 core_0_pif_pms_constrain_rtcfast_spltaddr_world_1 11 11 read-write CORE_0_PIF_PMS_CONSTRAIN_10 SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG 0x100 0x20 0x00000FFF CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L core_0_pif_pms_constrain_rtcfast_world_0_l 0 3 read-write CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H core_0_pif_pms_constrain_rtcfast_world_0_h 3 3 read-write CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L core_0_pif_pms_constrain_rtcfast_world_1_l 6 3 read-write CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H core_0_pif_pms_constrain_rtcfast_world_1_h 9 3 read-write REGION_PMS_CONSTRAIN_0 SENSITIVE_REGION_PMS_CONSTRAIN_0_REG 0x104 0x20 REGION_PMS_CONSTRAIN_LOCK region_pms_constrain_lock 0 1 read-write REGION_PMS_CONSTRAIN_1 SENSITIVE_REGION_PMS_CONSTRAIN_1_REG 0x108 0x20 0x00003FFF REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 region_pms_constrain_world_0_area_0 0 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 region_pms_constrain_world_0_area_1 2 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 region_pms_constrain_world_0_area_2 4 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 region_pms_constrain_world_0_area_3 6 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 region_pms_constrain_world_0_area_4 8 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 region_pms_constrain_world_0_area_5 10 2 read-write REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 region_pms_constrain_world_0_area_6 12 2 read-write REGION_PMS_CONSTRAIN_2 SENSITIVE_REGION_PMS_CONSTRAIN_2_REG 0x10C 0x20 0x00003FFF REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 region_pms_constrain_world_1_area_0 0 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 region_pms_constrain_world_1_area_1 2 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 region_pms_constrain_world_1_area_2 4 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 region_pms_constrain_world_1_area_3 6 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 region_pms_constrain_world_1_area_4 8 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 region_pms_constrain_world_1_area_5 10 2 read-write REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 region_pms_constrain_world_1_area_6 12 2 read-write REGION_PMS_CONSTRAIN_3 SENSITIVE_REGION_PMS_CONSTRAIN_3_REG 0x110 0x20 REGION_PMS_CONSTRAIN_ADDR_0 region_pms_constrain_addr_0 0 30 read-write REGION_PMS_CONSTRAIN_4 SENSITIVE_REGION_PMS_CONSTRAIN_4_REG 0x114 0x20 REGION_PMS_CONSTRAIN_ADDR_1 region_pms_constrain_addr_1 0 30 read-write REGION_PMS_CONSTRAIN_5 SENSITIVE_REGION_PMS_CONSTRAIN_5_REG 0x118 0x20 REGION_PMS_CONSTRAIN_ADDR_2 region_pms_constrain_addr_2 0 30 read-write REGION_PMS_CONSTRAIN_6 SENSITIVE_REGION_PMS_CONSTRAIN_6_REG 0x11C 0x20 REGION_PMS_CONSTRAIN_ADDR_3 region_pms_constrain_addr_3 0 30 read-write REGION_PMS_CONSTRAIN_7 SENSITIVE_REGION_PMS_CONSTRAIN_7_REG 0x120 0x20 REGION_PMS_CONSTRAIN_ADDR_4 region_pms_constrain_addr_4 0 30 read-write REGION_PMS_CONSTRAIN_8 SENSITIVE_REGION_PMS_CONSTRAIN_8_REG 0x124 0x20 REGION_PMS_CONSTRAIN_ADDR_5 region_pms_constrain_addr_5 0 30 read-write REGION_PMS_CONSTRAIN_9 SENSITIVE_REGION_PMS_CONSTRAIN_9_REG 0x128 0x20 REGION_PMS_CONSTRAIN_ADDR_6 region_pms_constrain_addr_6 0 30 read-write REGION_PMS_CONSTRAIN_10 SENSITIVE_REGION_PMS_CONSTRAIN_10_REG 0x12C 0x20 REGION_PMS_CONSTRAIN_ADDR_7 region_pms_constrain_addr_7 0 30 read-write CORE_0_PIF_PMS_MONITOR_0 SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG 0x130 0x20 CORE_0_PIF_PMS_MONITOR_LOCK core_0_pif_pms_monitor_lock 0 1 read-write CORE_0_PIF_PMS_MONITOR_1 SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG 0x134 0x20 0x00000003 CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR core_0_pif_pms_monitor_violate_clr 0 1 read-write CORE_0_PIF_PMS_MONITOR_VIOLATE_EN core_0_pif_pms_monitor_violate_en 1 1 read-write CORE_0_PIF_PMS_MONITOR_2 SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG 0x138 0x20 CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR core_0_pif_pms_monitor_violate_intr 0 1 read-only CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 core_0_pif_pms_monitor_violate_status_hport_0 1 1 read-only CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE core_0_pif_pms_monitor_violate_status_hsize 2 3 read-only CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE core_0_pif_pms_monitor_violate_status_hwrite 5 1 read-only CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD core_0_pif_pms_monitor_violate_status_hworld 6 2 read-only CORE_0_PIF_PMS_MONITOR_3 SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG 0x13C 0x20 CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR core_0_pif_pms_monitor_violate_status_haddr 0 32 read-only CORE_0_PIF_PMS_MONITOR_4 SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG 0x140 0x20 0x00000003 CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR core_0_pif_pms_monitor_nonword_violate_clr 0 1 read-write CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN core_0_pif_pms_monitor_nonword_violate_en 1 1 read-write CORE_0_PIF_PMS_MONITOR_5 SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG 0x144 0x20 CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR core_0_pif_pms_monitor_nonword_violate_intr 0 1 read-only CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE core_0_pif_pms_monitor_nonword_violate_status_hsize 1 2 read-only CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD core_0_pif_pms_monitor_nonword_violate_status_hworld 3 2 read-only CORE_0_PIF_PMS_MONITOR_6 SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG 0x148 0x20 CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR core_0_pif_pms_monitor_nonword_violate_status_haddr 0 32 read-only BACKUP_BUS_PMS_CONSTRAIN_0 SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG 0x14C 0x20 BACKUP_BUS_PMS_CONSTRAIN_LOCK backup_bus_pms_constrain_lock 0 1 read-write BACKUP_BUS_PMS_CONSTRAIN_1 SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG 0x150 0x20 0xCF0FFFFF BACKUP_BUS_PMS_CONSTRAIN_UART backup_bus_pms_constrain_uart 0 2 read-write BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 backup_bus_pms_constrain_g0spi_1 2 2 read-write BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 backup_bus_pms_constrain_g0spi_0 4 2 read-write BACKUP_BUS_PMS_CONSTRAIN_GPIO backup_bus_pms_constrain_gpio 6 2 read-write BACKUP_BUS_PMS_CONSTRAIN_FE2 backup_bus_pms_constrain_fe2 8 2 read-write BACKUP_BUS_PMS_CONSTRAIN_FE backup_bus_pms_constrain_fe 10 2 read-write BACKUP_BUS_PMS_CONSTRAIN_TIMER backup_bus_pms_constrain_timer 12 2 read-write BACKUP_BUS_PMS_CONSTRAIN_RTC backup_bus_pms_constrain_rtc 14 2 read-write BACKUP_BUS_PMS_CONSTRAIN_IO_MUX backup_bus_pms_constrain_io_mux 16 2 read-write BACKUP_BUS_PMS_CONSTRAIN_WDG backup_bus_pms_constrain_wdg 18 2 read-write BACKUP_BUS_PMS_CONSTRAIN_MISC backup_bus_pms_constrain_misc 24 2 read-write BACKUP_BUS_PMS_CONSTRAIN_I2C backup_bus_pms_constrain_i2c 26 2 read-write BACKUP_BUS_PMS_CONSTRAIN_UART1 backup_bus_pms_constrain_uart1 30 2 read-write BACKUP_BUS_PMS_CONSTRAIN_2 SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG 0x154 0x20 0xFCC30CF3 BACKUP_BUS_PMS_CONSTRAIN_BT backup_bus_pms_constrain_bt 0 2 read-write BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 backup_bus_pms_constrain_i2c_ext0 4 2 read-write BACKUP_BUS_PMS_CONSTRAIN_UHCI0 backup_bus_pms_constrain_uhci0 6 2 read-write BACKUP_BUS_PMS_CONSTRAIN_RMT backup_bus_pms_constrain_rmt 10 2 read-write BACKUP_BUS_PMS_CONSTRAIN_LEDC backup_bus_pms_constrain_ledc 16 2 read-write BACKUP_BUS_PMS_CONSTRAIN_BB backup_bus_pms_constrain_bb 22 2 read-write BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP backup_bus_pms_constrain_timergroup 26 2 read-write BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 backup_bus_pms_constrain_timergroup1 28 2 read-write BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER backup_bus_pms_constrain_systimer 30 2 read-write BACKUP_BUS_PMS_CONSTRAIN_3 SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG 0x158 0x20 0x3CC0CC33 BACKUP_BUS_PMS_CONSTRAIN_SPI_2 backup_bus_pms_constrain_spi_2 0 2 read-write BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL backup_bus_pms_constrain_apb_ctrl 4 2 read-write BACKUP_BUS_PMS_CONSTRAIN_CAN backup_bus_pms_constrain_can 10 2 read-write BACKUP_BUS_PMS_CONSTRAIN_I2S1 backup_bus_pms_constrain_i2s1 14 2 read-write BACKUP_BUS_PMS_CONSTRAIN_RWBT backup_bus_pms_constrain_rwbt 22 2 read-write BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC backup_bus_pms_constrain_wifimac 26 2 read-write BACKUP_BUS_PMS_CONSTRAIN_PWR backup_bus_pms_constrain_pwr 28 2 read-write BACKUP_BUS_PMS_CONSTRAIN_4 SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG 0x15C 0x20 0x0000F3FC BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP backup_bus_pms_constrain_usb_wrap 2 2 read-write BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI backup_bus_pms_constrain_crypto_peri 4 2 read-write BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA backup_bus_pms_constrain_crypto_dma 6 2 read-write BACKUP_BUS_PMS_CONSTRAIN_APB_ADC backup_bus_pms_constrain_apb_adc 8 2 read-write BACKUP_BUS_PMS_CONSTRAIN_BT_PWR backup_bus_pms_constrain_bt_pwr 12 2 read-write BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE backup_bus_pms_constrain_usb_device 14 2 read-write BACKUP_BUS_PMS_MONITOR_0 SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG 0x160 0x20 BACKUP_BUS_PMS_MONITOR_LOCK backup_bus_pms_monitor_lock 0 1 read-write BACKUP_BUS_PMS_MONITOR_1 SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG 0x164 0x20 0x00000003 BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR backup_bus_pms_monitor_violate_clr 0 1 read-write BACKUP_BUS_PMS_MONITOR_VIOLATE_EN backup_bus_pms_monitor_violate_en 1 1 read-write BACKUP_BUS_PMS_MONITOR_2 SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG 0x168 0x20 BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR backup_bus_pms_monitor_violate_intr 0 1 read-only BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS backup_bus_pms_monitor_violate_status_htrans 1 2 read-only BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE backup_bus_pms_monitor_violate_status_hsize 3 3 read-only BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE backup_bus_pms_monitor_violate_status_hwrite 6 1 read-only BACKUP_BUS_PMS_MONITOR_3 SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG 0x16C 0x20 BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR backup_bus_pms_monitor_violate_haddr 0 32 read-only CLOCK_GATE SENSITIVE_CLOCK_GATE_REG_REG 0x170 0x20 0x00000001 CLK_EN clk_en 0 1 read-write DATE SENSITIVE_DATE_REG 0xFFC 0x20 0x02010200 DATE reg_date 0 28 read-write SHA SHA (Secure Hash Algorithm) Accelerator SHA 0x6003B000 0x0 0xB0 registers SHA 49 MODE Initial configuration register. 0x0 0x20 MODE Sha mode. 0 3 read-write T_STRING SHA 512/t configuration register 0. 0x4 0x20 T_STRING Sha t_string (used if and only if mode == SHA_512/t). 0 32 read-write T_LENGTH SHA 512/t configuration register 1. 0x8 0x20 T_LENGTH Sha t_length (used if and only if mode == SHA_512/t). 0 6 read-write DMA_BLOCK_NUM DMA configuration register 0. 0xC 0x20 DMA_BLOCK_NUM Dma-sha block number. 0 6 read-write START Typical SHA configuration register 0. 0x10 0x20 START Reserved. 1 31 read-only CONTINUE Typical SHA configuration register 1. 0x14 0x20 CONTINUE Reserved. 1 31 read-only BUSY Busy register. 0x18 0x20 STATE Sha busy state. 1'b0: idle. 1'b1: busy. 0 1 read-only DMA_START DMA configuration register 1. 0x1C 0x20 DMA_START Start dma-sha. 0 1 write-only DMA_CONTINUE DMA configuration register 2. 0x20 0x20 DMA_CONTINUE Continue dma-sha. 0 1 write-only CLEAR_IRQ Interrupt clear register. 0x24 0x20 CLEAR_INTERRUPT Clear sha interrupt. 0 1 write-only IRQ_ENA Interrupt enable register. 0x28 0x20 INTERRUPT_ENA Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. 0 1 read-write DATE Date register. 0x2C 0x20 0x20200616 DATE Sha date information/ sha version information. 0 30 read-write 64 0x1 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 0x8 64 0x1 M_MEM[%s] Sha M memory which contains message. 0x80 0x8 SPI0 SPI (Serial Peripheral Interface) Controller SPI0 0x60003000 0x0 0x48 registers CTRL SPI0 control register. 0x8 0x20 0x002C2000 FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write FASTRD_MODE This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. 13 1 read-write FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write CTRL1 SPI0 control1 register. 0xC 0x20 CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write RXFIFO_RST SPI0 RX FIFO reset signal. 30 1 write-only CTRL2 SPI0 control2 register. 0x10 0x20 0x00000021 CS_SETUP_TIME (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. 0 5 read-write CS_HOLD_TIME Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. 5 5 read-write CS_HOLD_DELAY These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. 25 6 read-write SYNC_RESET The FSM will be reset. 31 1 write-only CLOCK SPI clock division control register. 0x14 0x20 0x00030103 CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write CLK_EQU_SYSCLK Set this bit in 1-division mode. 31 1 read-write USER SPI0 user register. 0x18 0x20 CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. 6 1 read-write CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. 7 1 read-write CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. 26 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write USER1 SPI0 user1 register. 0x1C 0x20 0x5C000007 USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write USER2 SPI0 user2 register. 0x20 0x20 0x70000000 USR_COMMAND_VALUE The value of command. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write RD_STATUS SPI0 read control register. 0x2C 0x20 WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write MISC SPI0 misc register 0x34 0x20 TRANS_END The bit is used to indicate the spi0_mst_st controlled transmitting is done. 3 1 read-write TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. 4 1 read-write CSPI_ST_TRANS_END The bit is used to indicate the spi0_slv_st controlled transmitting is done. 5 1 read-write CSPI_ST_TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. 6 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 read-write CACHE_FCTRL SPI0 bit mode control register. 0x3C 0x20 CACHE_REQ_EN For SPI0, Cache access enable, 1: enable, 0:disable. 0 1 read-write CACHE_USR_ADDR_4BYTE For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write CACHE_FLASH_USR_CMD For SPI0, cache read flash for user define command, 1: enable, 0:disable. 2 1 read-write FDIN_DUAL For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write FDOUT_DUAL For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write FADDR_DUAL For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write FDIN_QUAD For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write FDOUT_QUAD For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write FADDR_QUAD For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write FSM SPI0 FSM status register 0x54 0x20 0x00000200 CSPI_ST The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 0 4 read-only EM_ST The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. 4 3 read-only CSPI_LOCK_DELAY_TIME The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. 7 5 read-write TIMING_CALI SPI0 timing calibration register 0xA8 0x20 0x00000001 TIMING_CLK_ENA The bit is used to enable timing adjust clock for all reading operations. 0 1 read-write TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-write EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-write DIN_MODE SPI0 input delay mode control register 0xAC 0x20 DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 2 read-write DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 2 2 read-write DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 4 2 read-write DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 2 read-write DIN_NUM SPI0 input delay number control register 0xB0 0x20 DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 2 read-write DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 2 read-write DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 4 2 read-write DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 6 2 read-write DOUT_MODE SPI0 output delay mode control register 0xB4 0x20 DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 read-write DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 read-write DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 read-write DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 read-write CLOCK_GATE SPI0 clk_gate register 0xDC 0x20 0x00000001 CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write CORE_CLK_SEL SPI0 module clock select register 0xE0 0x20 SPI01_CLK_SEL When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. 0 2 read-write DATE Version control register 0x3FC 0x20 0x02007130 DATE SPI register version. 0 28 read-write SPI1 SPI (Serial Peripheral Interface) Controller SPI1 0x60002000 0x0 0xA8 registers CMD SPI1 memory command register 0x0 0x20 SPI1_MST_ST The current status of SPI1 master FSM. 0 4 read-only MSPI_ST The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 4 4 read-only FLASH_PE In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. 17 1 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-write FLASH_HPM Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. 19 1 read-write FLASH_RES This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. 20 1 read-write FLASH_DP Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 21 1 read-write FLASH_CE Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 22 1 read-write FLASH_BE Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 23 1 read-write FLASH_SE Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 24 1 read-write FLASH_PP Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. 25 1 read-write FLASH_WRSR Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 26 1 read-write FLASH_RDSR Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 27 1 read-write FLASH_RDID Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 28 1 read-write FLASH_WRDI Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 29 1 read-write FLASH_WREN Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 30 1 read-write FLASH_READ Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 31 1 read-write ADDR SPI1 address register 0x4 0x20 USR_ADDR_VALUE In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. 0 32 read-write CTRL SPI1 control register. 0x8 0x20 0x002CA000 FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write FCS_CRC_EN For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. 10 1 read-write TX_CRC_EN For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable 11 1 read-write FASTRD_MODE This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. 13 1 read-write FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write RESANDRES The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. 15 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write WRSR_2B two bytes data will be written to status register when it is set. 1: enable 0: disable. 22 1 read-write FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write CTRL1 SPI1 control1 register. 0xC 0x20 0x00000FFC CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write CS_HOLD_DLY_RES After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. 2 10 read-write CTRL2 SPI1 control2 register. 0x10 0x20 SYNC_RESET The FSM will be reset. 31 1 write-only CLOCK SPI1 clock division control register. 0x14 0x20 0x00030103 CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write CLK_EQU_SYSCLK reserved 31 1 read-write USER SPI1 user register. 0x18 0x20 0x80000000 CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write FWRITE_DUAL In the write operations read-data phase apply 2 signals 12 1 read-write FWRITE_QUAD In the write operations read-data phase apply 4 signals 13 1 read-write FWRITE_DIO In the write operations address phase and read-data phase apply 2 signals. 14 1 read-write FWRITE_QIO In the write operations address phase and read-data phase apply 4 signals. 15 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 25 1 read-write USR_DUMMY_IDLE SPI clock is disable in dummy phase when the bit is enable. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. 31 1 read-write USER1 SPI1 user1 register. 0x1C 0x20 0x5C000007 USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write USER2 SPI1 user2 register. 0x20 0x20 0x70000000 USR_COMMAND_VALUE The value of command. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write MOSI_DLEN SPI1 send data bit length control register. 0x24 0x20 USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). 0 10 read-write MISO_DLEN SPI1 receive data bit length control register. 0x28 0x20 USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). 0 10 read-write RD_STATUS SPI1 status register. 0x2C 0x20 STATUS The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. 0 16 read-write WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write MISC SPI1 misc register 0x34 0x20 0x00000002 CS0_DIS SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. 0 1 read-write CS1_DIS SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. 1 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 read-write TX_CRC SPI1 TX CRC data register. 0x38 0x20 0xFFFFFFFF DATA For SPI1, the value of crc32. 0 32 read-only CACHE_FCTRL SPI1 bit mode control register. 0x3C 0x20 CACHE_USR_ADDR_4BYTE For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write FDIN_DUAL For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write FDOUT_DUAL For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write FADDR_DUAL For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write FDIN_QUAD For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write FDOUT_QUAD For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write FADDR_QUAD For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write W0 SPI1 memory data buffer0 0x58 0x20 BUF0 data buffer 0 32 read-write W1 SPI1 memory data buffer1 0x5C 0x20 BUF1 data buffer 0 32 read-write W2 SPI1 memory data buffer2 0x60 0x20 BUF2 data buffer 0 32 read-write W3 SPI1 memory data buffer3 0x64 0x20 BUF3 data buffer 0 32 read-write W4 SPI1 memory data buffer4 0x68 0x20 BUF4 data buffer 0 32 read-write W5 SPI1 memory data buffer5 0x6C 0x20 BUF5 data buffer 0 32 read-write W6 SPI1 memory data buffer6 0x70 0x20 BUF6 data buffer 0 32 read-write W7 SPI1 memory data buffer7 0x74 0x20 BUF7 data buffer 0 32 read-write W8 SPI1 memory data buffer8 0x78 0x20 BUF8 data buffer 0 32 read-write W9 SPI1 memory data buffer9 0x7C 0x20 BUF9 data buffer 0 32 read-write W10 SPI1 memory data buffer10 0x80 0x20 BUF10 data buffer 0 32 read-write W11 SPI1 memory data buffer11 0x84 0x20 BUF11 data buffer 0 32 read-write W12 SPI1 memory data buffer12 0x88 0x20 BUF12 data buffer 0 32 read-write W13 SPI1 memory data buffer13 0x8C 0x20 BUF13 data buffer 0 32 read-write W14 SPI1 memory data buffer14 0x90 0x20 BUF14 data buffer 0 32 read-write W15 SPI1 memory data buffer15 0x94 0x20 BUF15 data buffer 0 32 read-write FLASH_WAITI_CTRL SPI1 wait idle control register 0x98 0x20 0x00000014 WAITI_DUMMY The dummy phase enable when wait flash idle (RDSR) 1 1 read-write WAITI_CMD The command to wait flash idle(RDSR). 2 8 read-write WAITI_DUMMY_CYCLELEN The dummy cycle length when wait flash idle(RDSR). 10 6 read-write FLASH_SUS_CTRL SPI1 flash suspend control register 0x9C 0x20 0x08002000 FLASH_PER program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 0 1 read-write FLASH_PES program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 1 1 read-write FLASH_PER_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. 2 1 read-write FLASH_PES_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. 3 1 read-write PES_PER_EN Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. 4 1 read-write FLASH_PES_EN Set this bit to enable Auto-suspending function. 5 1 read-write PESR_END_MSK The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. 6 16 read-write RD_SUS_2B 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit 22 1 read-write PER_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. 23 1 read-write PES_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. 24 1 read-write SUS_TIMEOUT_CNT When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. 25 7 read-write FLASH_SUS_CMD SPI1 flash suspend command register 0xA0 0x20 0x0005757A FLASH_PER_COMMAND Program/Erase resume command. 0 8 read-write FLASH_PES_COMMAND Program/Erase suspend command. 8 8 read-write WAIT_PESR_COMMAND Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. 16 16 read-write SUS_STATUS SPI1 flash suspend status register 0xA4 0x20 FLASH_SUS The status of flash suspend, only used in SPI1. 0 1 read-write WAIT_PESR_CMD_2B 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. 1 1 read-write FLASH_HPM_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. 2 1 read-write FLASH_RES_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. 3 1 read-write FLASH_DP_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. 4 1 read-write FLASH_PER_DLY_128 Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. 5 1 read-write FLASH_PES_DLY_128 Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. 6 1 read-write SPI0_LOCK_EN 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. 7 1 read-write TIMING_CALI SPI1 timing control register 0xA8 0x20 TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-write EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-write INT_ENA SPI1 interrupt enable register 0xC0 0x20 PER_END_INT_ENA The enable bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-write PES_END_INT_ENA The enable bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-write WPE_END_INT_ENA The enable bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-write SLV_ST_END_INT_ENA The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-write MST_ST_END_INT_ENA The enable bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-write INT_CLR SPI1 interrupt clear register 0xC4 0x20 PER_END_INT_CLR The clear bit for SPI_MEM_PER_END_INT interrupt. 0 1 write-only PES_END_INT_CLR The clear bit for SPI_MEM_PES_END_INT interrupt. 1 1 write-only WPE_END_INT_CLR The clear bit for SPI_MEM_WPE_END_INT interrupt. 2 1 write-only SLV_ST_END_INT_CLR The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 write-only MST_ST_END_INT_CLR The clear bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 write-only INT_RAW SPI1 interrupt raw register 0xC8 0x20 PER_END_INT_RAW The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. 0 1 read-only PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. 1 1 read-only WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 read-only SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 read-only MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 read-only INT_ST SPI1 interrupt status register 0xCC 0x20 PER_END_INT_ST The status bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-only PES_END_INT_ST The status bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-only WPE_END_INT_ST The status bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-only SLV_ST_END_INT_ST The status bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-only MST_ST_END_INT_ST The status bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-only CLOCK_GATE SPI1 clk_gate register 0xDC 0x20 0x00000001 CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write DATE Version control register 0x3FC 0x20 0x02007170 DATE Version control register 0 28 read-write SPI2 SPI (Serial Peripheral Interface) Controller SPI2 0x60024000 0x0 0x94 registers SPI2 19 CMD Command control register 0x0 0x20 CONF_BITLEN Define the APB cycles of SPI_CONF state. Can be configured in CONF state. 0 18 read-write UPDATE Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. 23 1 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. 24 1 read-write ADDR Address value register 0x4 0x20 USR_ADDR_VALUE Address to slave. Can be configured in CONF state. 0 32 read-write CTRL SPI control register 0x8 0x20 0x003C0000 DUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. 3 1 read-write FADDR_DUAL Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 5 1 read-write FADDR_QUAD Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 6 1 read-write FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 8 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 9 1 read-write FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. 14 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. 15 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. 19 1 read-write HOLD_POL SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 20 1 read-write WP_POL Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 21 1 read-write RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. 25 1 read-write WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. 26 1 read-write CLOCK SPI clock control register 0xC 0x20 0x80003043 CLKCNT_L In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. 0 6 read-write CLKCNT_H In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. 6 6 read-write CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. 12 6 read-write CLKDIV_PRE In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 18 4 read-write CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. 31 1 read-write USER SPI USER control register 0x10 0x20 0x800000C0 DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. 0 1 read-write QPI_MODE Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. 3 1 read-write TSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. 5 1 read-write CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write RSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. 8 1 read-write CK_OUT_EDGE the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. 9 1 read-write FWRITE_DUAL In the write operations read-data phase apply 2 signals. Can be configured in CONF state. 12 1 read-write FWRITE_QUAD In the write operations read-data phase apply 4 signals. Can be configured in CONF state. 13 1 read-write USR_CONF_NXT 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. 15 1 read-write SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. 17 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 25 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. Can be configured in CONF state. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. Can be configured in CONF state. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. Can be configured in CONF state. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. Can be configured in CONF state. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. Can be configured in CONF state. 31 1 read-write USER1 SPI USER control register 1 0x14 0x20 0xB8410007 USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. 0 8 read-write MST_WFULL_ERR_END_EN 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 16 1 read-write CS_SETUP_TIME (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. 17 5 read-write CS_HOLD_TIME delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. 22 5 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. 27 5 read-write USER2 SPI USER control register 2 0x18 0x20 0x78000000 USR_COMMAND_VALUE The value of command. Can be configured in CONF state. 0 16 read-write MST_REMPTY_ERR_END_EN 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 27 1 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. 28 4 read-write MS_DLEN SPI data bit length control register 0x1C 0x20 MS_DATA_BITLEN The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. 0 18 read-write MISC SPI misc register 0x20 0x20 0x0000003E CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. 0 1 read-write CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. 1 1 read-write CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. 2 1 read-write CS3_DIS SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. 3 1 read-write CS4_DIS SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. 4 1 read-write CS5_DIS SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. 5 1 read-write CK_DIS 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 6 1 read-write MASTER_CS_POL In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. 7 6 read-write SLAVE_CS_POL spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. 23 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. 29 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. Can be configured in CONF state. 30 1 read-write QUAD_DIN_PIN_SWAP 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. 31 1 read-write DIN_MODE SPI input delay mode configuration 0x24 0x20 DIN0_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 read-write DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 read-write DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 read-write DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 read-write TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 read-write DIN_NUM SPI input delay number configuration 0x28 0x20 DIN0_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write DOUT_MODE SPI output delay mode configuration 0x2C 0x20 DOUT0_MODE The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 read-write DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 read-write DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 read-write DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 read-write DMA_CONF SPI DMA control register 0x30 0x20 DMA_SLV_SEG_TRANS_EN Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 18 1 read-write SLV_RX_SEG_TRANS_CLR_EN 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. 19 1 read-write SLV_TX_SEG_TRANS_CLR_EN 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. 20 1 read-write RX_EOF_EN 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. 21 1 read-write DMA_RX_ENA Set this bit to enable SPI DMA controlled receive data mode. 27 1 read-write DMA_TX_ENA Set this bit to enable SPI DMA controlled send data mode. 28 1 read-write RX_AFIFO_RST Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. 29 1 write-only BUF_AFIFO_RST Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. 30 1 write-only DMA_AFIFO_RST Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. 31 1 write-only DMA_INT_ENA SPI DMA interrupt enable register 0x34 0x20 DMA_INFIFO_FULL_ERR_INT_ENA The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-write DMA_OUTFIFO_EMPTY_ERR_INT_ENA The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-write SLV_EX_QPI_INT_ENA The enable bit for SPI slave Ex_QPI interrupt. 2 1 read-write SLV_EN_QPI_INT_ENA The enable bit for SPI slave En_QPI interrupt. 3 1 read-write SLV_CMD7_INT_ENA The enable bit for SPI slave CMD7 interrupt. 4 1 read-write SLV_CMD8_INT_ENA The enable bit for SPI slave CMD8 interrupt. 5 1 read-write SLV_CMD9_INT_ENA The enable bit for SPI slave CMD9 interrupt. 6 1 read-write SLV_CMDA_INT_ENA The enable bit for SPI slave CMDA interrupt. 7 1 read-write SLV_RD_DMA_DONE_INT_ENA The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-write SLV_WR_DMA_DONE_INT_ENA The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-write SLV_RD_BUF_DONE_INT_ENA The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-write SLV_WR_BUF_DONE_INT_ENA The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-write TRANS_DONE_INT_ENA The enable bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-write DMA_SEG_TRANS_DONE_INT_ENA The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-write SEG_MAGIC_ERR_INT_ENA The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-write SLV_BUF_ADDR_ERR_INT_ENA The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-write SLV_CMD_ERR_INT_ENA The enable bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-write MST_RX_AFIFO_WFULL_ERR_INT_ENA The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-write MST_TX_AFIFO_REMPTY_ERR_INT_ENA The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-write APP2_INT_ENA The enable bit for SPI_APP2_INT interrupt. 19 1 read-write APP1_INT_ENA The enable bit for SPI_APP1_INT interrupt. 20 1 read-write DMA_INT_CLR SPI DMA interrupt clear register 0x38 0x20 DMA_INFIFO_FULL_ERR_INT_CLR The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only DMA_OUTFIFO_EMPTY_ERR_INT_CLR The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only SLV_EX_QPI_INT_CLR The clear bit for SPI slave Ex_QPI interrupt. 2 1 write-only SLV_EN_QPI_INT_CLR The clear bit for SPI slave En_QPI interrupt. 3 1 write-only SLV_CMD7_INT_CLR The clear bit for SPI slave CMD7 interrupt. 4 1 write-only SLV_CMD8_INT_CLR The clear bit for SPI slave CMD8 interrupt. 5 1 write-only SLV_CMD9_INT_CLR The clear bit for SPI slave CMD9 interrupt. 6 1 write-only SLV_CMDA_INT_CLR The clear bit for SPI slave CMDA interrupt. 7 1 write-only SLV_RD_DMA_DONE_INT_CLR The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only SLV_WR_DMA_DONE_INT_CLR The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only SLV_RD_BUF_DONE_INT_CLR The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only SLV_WR_BUF_DONE_INT_CLR The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only TRANS_DONE_INT_CLR The clear bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only DMA_SEG_TRANS_DONE_INT_CLR The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only SEG_MAGIC_ERR_INT_CLR The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only SLV_BUF_ADDR_ERR_INT_CLR The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only SLV_CMD_ERR_INT_CLR The clear bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only MST_RX_AFIFO_WFULL_ERR_INT_CLR The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only MST_TX_AFIFO_REMPTY_ERR_INT_CLR The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only APP2_INT_CLR The clear bit for SPI_APP2_INT interrupt. 19 1 write-only APP1_INT_CLR The clear bit for SPI_APP1_INT interrupt. 20 1 write-only DMA_INT_RAW SPI DMA interrupt raw register 0x3C 0x20 DMA_INFIFO_FULL_ERR_INT_RAW 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. 0 1 read-write DMA_OUTFIFO_EMPTY_ERR_INT_RAW 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. 1 1 read-write SLV_EX_QPI_INT_RAW The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. 2 1 read-write SLV_EN_QPI_INT_RAW The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. 3 1 read-write SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. 4 1 read-write SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. 5 1 read-write SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. 6 1 read-write SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. 7 1 read-write SLV_RD_DMA_DONE_INT_RAW The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. 8 1 read-write SLV_WR_DMA_DONE_INT_RAW The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. 9 1 read-write SLV_RD_BUF_DONE_INT_RAW The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. 10 1 read-write SLV_WR_BUF_DONE_INT_RAW The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. 11 1 read-write TRANS_DONE_INT_RAW The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. 12 1 read-write DMA_SEG_TRANS_DONE_INT_RAW The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. 13 1 read-write SEG_MAGIC_ERR_INT_RAW The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. 14 1 read-write SLV_BUF_ADDR_ERR_INT_RAW The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. 15 1 read-write SLV_CMD_ERR_INT_RAW The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. 16 1 read-write MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. 17 1 read-write MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 18 1 read-write APP2_INT_RAW The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application. 19 1 read-write APP1_INT_RAW The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application. 20 1 read-write DMA_INT_ST SPI DMA interrupt status register 0x40 0x20 DMA_INFIFO_FULL_ERR_INT_ST The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-only DMA_OUTFIFO_EMPTY_ERR_INT_ST The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-only SLV_EX_QPI_INT_ST The status bit for SPI slave Ex_QPI interrupt. 2 1 read-only SLV_EN_QPI_INT_ST The status bit for SPI slave En_QPI interrupt. 3 1 read-only SLV_CMD7_INT_ST The status bit for SPI slave CMD7 interrupt. 4 1 read-only SLV_CMD8_INT_ST The status bit for SPI slave CMD8 interrupt. 5 1 read-only SLV_CMD9_INT_ST The status bit for SPI slave CMD9 interrupt. 6 1 read-only SLV_CMDA_INT_ST The status bit for SPI slave CMDA interrupt. 7 1 read-only SLV_RD_DMA_DONE_INT_ST The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-only SLV_WR_DMA_DONE_INT_ST The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-only SLV_RD_BUF_DONE_INT_ST The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-only SLV_WR_BUF_DONE_INT_ST The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-only TRANS_DONE_INT_ST The status bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-only DMA_SEG_TRANS_DONE_INT_ST The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-only SEG_MAGIC_ERR_INT_ST The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-only SLV_BUF_ADDR_ERR_INT_ST The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-only SLV_CMD_ERR_INT_ST The status bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-only MST_RX_AFIFO_WFULL_ERR_INT_ST The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-only MST_TX_AFIFO_REMPTY_ERR_INT_ST The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-only APP2_INT_ST The status bit for SPI_APP2_INT interrupt. 19 1 read-only APP1_INT_ST The status bit for SPI_APP1_INT interrupt. 20 1 read-only W0 SPI CPU-controlled buffer0 0x98 0x20 BUF0 data buffer 0 32 read-write W1 SPI CPU-controlled buffer1 0x9C 0x20 BUF1 data buffer 0 32 read-write W2 SPI CPU-controlled buffer2 0xA0 0x20 BUF2 data buffer 0 32 read-write W3 SPI CPU-controlled buffer3 0xA4 0x20 BUF3 data buffer 0 32 read-write W4 SPI CPU-controlled buffer4 0xA8 0x20 BUF4 data buffer 0 32 read-write W5 SPI CPU-controlled buffer5 0xAC 0x20 BUF5 data buffer 0 32 read-write W6 SPI CPU-controlled buffer6 0xB0 0x20 BUF6 data buffer 0 32 read-write W7 SPI CPU-controlled buffer7 0xB4 0x20 BUF7 data buffer 0 32 read-write W8 SPI CPU-controlled buffer8 0xB8 0x20 BUF8 data buffer 0 32 read-write W9 SPI CPU-controlled buffer9 0xBC 0x20 BUF9 data buffer 0 32 read-write W10 SPI CPU-controlled buffer10 0xC0 0x20 BUF10 data buffer 0 32 read-write W11 SPI CPU-controlled buffer11 0xC4 0x20 BUF11 data buffer 0 32 read-write W12 SPI CPU-controlled buffer12 0xC8 0x20 BUF12 data buffer 0 32 read-write W13 SPI CPU-controlled buffer13 0xCC 0x20 BUF13 data buffer 0 32 read-write W14 SPI CPU-controlled buffer14 0xD0 0x20 BUF14 data buffer 0 32 read-write W15 SPI CPU-controlled buffer15 0xD4 0x20 BUF15 data buffer 0 32 read-write SLAVE SPI slave control register 0xE0 0x20 0x02800000 CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. 0 2 read-write CLK_MODE_13 {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 2 1 read-write RSCK_DATA_OUT It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge 3 1 read-write SLV_RDDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others 8 1 read-write SLV_WRDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others 9 1 read-write SLV_RDBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others 10 1 read-write SLV_WRBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others 11 1 read-write DMA_SEG_MAGIC_VALUE The magic value of BM table in master DMA seg-trans. 22 4 read-write MODE Set SPI work mode. 1: slave mode 0: master mode. 26 1 read-write SOFT_RESET Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. 27 1 write-only USR_CONF 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. 28 1 read-write SLAVE1 SPI slave control register 1 0xE4 0x20 SLV_DATA_BITLEN The transferred data bit length in SPI slave FD and HD mode. 0 18 read-write SLV_LAST_COMMAND In the slave mode it is the value of command. 18 8 read-write SLV_LAST_ADDR In the slave mode it is the value of address. 26 6 read-write CLK_GATE SPI module clock and register clock control 0xE8 0x20 CLK_EN Set this bit to enable clk gate 0 1 read-write MST_CLK_ACTIVE Set this bit to power on the SPI module clock. 1 1 read-write MST_CLK_SEL This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. 2 1 read-write DATE Version control 0xF0 0x20 0x02007220 DATE SPI register version. 0 28 read-write SYSTEM System SYSTEM 0x600C0000 0x0 0xA0 registers CPU_PERI_CLK_EN cpu_peripheral clock gating register 0x0 0x20 CLK_EN_ASSIST_DEBUG reg_clk_en_assist_debug 6 1 read-write CLK_EN_DEDICATED_GPIO reg_clk_en_dedicated_gpio 7 1 read-write CPU_PERI_RST_EN cpu_peripheral reset register 0x4 0x20 0x000000C0 RST_EN_ASSIST_DEBUG reg_rst_en_assist_debug 6 1 read-write RST_EN_DEDICATED_GPIO reg_rst_en_dedicated_gpio 7 1 read-write CPU_PER_CONF cpu clock config register 0x8 0x20 0x0000000C CPUPERIOD_SEL reg_cpuperiod_sel 0 2 read-write PLL_FREQ_SEL reg_pll_freq_sel 2 1 read-write CPU_WAIT_MODE_FORCE_ON reg_cpu_wait_mode_force_on 3 1 read-write CPU_WAITI_DELAY_NUM reg_cpu_waiti_delay_num 4 4 read-write MEM_PD_MASK memory power down mask register 0xC 0x20 0x00000001 LSLP_MEM_PD_MASK reg_lslp_mem_pd_mask 0 1 read-write PERIP_CLK_EN0 peripheral clock gating register 0x10 0x20 0xF9C1E06F TIMERS_CLK_EN reg_timers_clk_en 0 1 read-write SPI01_CLK_EN reg_spi01_clk_en 1 1 read-write UART_CLK_EN reg_uart_clk_en 2 1 read-write WDG_CLK_EN reg_wdg_clk_en 3 1 read-write I2S0_CLK_EN reg_i2s0_clk_en 4 1 read-write UART1_CLK_EN reg_uart1_clk_en 5 1 read-write SPI2_CLK_EN reg_spi2_clk_en 6 1 read-write I2C_EXT0_CLK_EN reg_ext0_clk_en 7 1 read-write UHCI0_CLK_EN reg_uhci0_clk_en 8 1 read-write RMT_CLK_EN reg_rmt_clk_en 9 1 read-write PCNT_CLK_EN reg_pcnt_clk_en 10 1 read-write LEDC_CLK_EN reg_ledc_clk_en 11 1 read-write UHCI1_CLK_EN reg_uhci1_clk_en 12 1 read-write TIMERGROUP_CLK_EN reg_timergroup_clk_en 13 1 read-write EFUSE_CLK_EN reg_efuse_clk_en 14 1 read-write TIMERGROUP1_CLK_EN reg_timergroup1_clk_en 15 1 read-write SPI3_CLK_EN reg_spi3_clk_en 16 1 read-write PWM0_CLK_EN reg_pwm0_clk_en 17 1 read-write EXT1_CLK_EN reg_ext1_clk_en 18 1 read-write CAN_CLK_EN reg_can_clk_en 19 1 read-write PWM1_CLK_EN reg_pwm1_clk_en 20 1 read-write I2S1_CLK_EN reg_i2s1_clk_en 21 1 read-write SPI2_DMA_CLK_EN reg_spi2_dma_clk_en 22 1 read-write USB_DEVICE_CLK_EN reg_usb_device_clk_en 23 1 read-write UART_MEM_CLK_EN reg_uart_mem_clk_en 24 1 read-write PWM2_CLK_EN reg_pwm2_clk_en 25 1 read-write PWM3_CLK_EN reg_pwm3_clk_en 26 1 read-write SPI3_DMA_CLK_EN reg_spi3_dma_clk_en 27 1 read-write APB_SARADC_CLK_EN reg_apb_saradc_clk_en 28 1 read-write SYSTIMER_CLK_EN reg_systimer_clk_en 29 1 read-write ADC2_ARB_CLK_EN reg_adc2_arb_clk_en 30 1 read-write SPI4_CLK_EN reg_spi4_clk_en 31 1 read-write PERIP_CLK_EN1 peripheral clock gating register 0x14 0x20 0x00000200 CRYPTO_AES_CLK_EN reg_crypto_aes_clk_en 1 1 read-write CRYPTO_SHA_CLK_EN reg_crypto_sha_clk_en 2 1 read-write CRYPTO_RSA_CLK_EN reg_crypto_rsa_clk_en 3 1 read-write CRYPTO_DS_CLK_EN reg_crypto_ds_clk_en 4 1 read-write CRYPTO_HMAC_CLK_EN reg_crypto_hmac_clk_en 5 1 read-write DMA_CLK_EN reg_dma_clk_en 6 1 read-write SDIO_HOST_CLK_EN reg_sdio_host_clk_en 7 1 read-write LCD_CAM_CLK_EN reg_lcd_cam_clk_en 8 1 read-write UART2_CLK_EN reg_uart2_clk_en 9 1 read-write TSENS_CLK_EN reg_tsens_clk_en 10 1 read-write PERIP_RST_EN0 reserved 0x18 0x20 TIMERS_RST reg_timers_rst 0 1 read-write SPI01_RST reg_spi01_rst 1 1 read-write UART_RST reg_uart_rst 2 1 read-write WDG_RST reg_wdg_rst 3 1 read-write I2S0_RST reg_i2s0_rst 4 1 read-write UART1_RST reg_uart1_rst 5 1 read-write SPI2_RST reg_spi2_rst 6 1 read-write I2C_EXT0_RST reg_ext0_rst 7 1 read-write UHCI0_RST reg_uhci0_rst 8 1 read-write RMT_RST reg_rmt_rst 9 1 read-write PCNT_RST reg_pcnt_rst 10 1 read-write LEDC_RST reg_ledc_rst 11 1 read-write UHCI1_RST reg_uhci1_rst 12 1 read-write TIMERGROUP_RST reg_timergroup_rst 13 1 read-write EFUSE_RST reg_efuse_rst 14 1 read-write TIMERGROUP1_RST reg_timergroup1_rst 15 1 read-write SPI3_RST reg_spi3_rst 16 1 read-write PWM0_RST reg_pwm0_rst 17 1 read-write EXT1_RST reg_ext1_rst 18 1 read-write CAN_RST reg_can_rst 19 1 read-write PWM1_RST reg_pwm1_rst 20 1 read-write I2S1_RST reg_i2s1_rst 21 1 read-write SPI2_DMA_RST reg_spi2_dma_rst 22 1 read-write USB_DEVICE_RST reg_usb_device_rst 23 1 read-write UART_MEM_RST reg_uart_mem_rst 24 1 read-write PWM2_RST reg_pwm2_rst 25 1 read-write PWM3_RST reg_pwm3_rst 26 1 read-write SPI3_DMA_RST reg_spi3_dma_rst 27 1 read-write APB_SARADC_RST reg_apb_saradc_rst 28 1 read-write SYSTIMER_RST reg_systimer_rst 29 1 read-write ADC2_ARB_RST reg_adc2_arb_rst 30 1 read-write SPI4_RST reg_spi4_rst 31 1 read-write PERIP_RST_EN1 peripheral reset register 0x1C 0x20 0x000001FE CRYPTO_AES_RST reg_crypto_aes_rst 1 1 read-write CRYPTO_SHA_RST reg_crypto_sha_rst 2 1 read-write CRYPTO_RSA_RST reg_crypto_rsa_rst 3 1 read-write CRYPTO_DS_RST reg_crypto_ds_rst 4 1 read-write CRYPTO_HMAC_RST reg_crypto_hmac_rst 5 1 read-write DMA_RST reg_dma_rst 6 1 read-write SDIO_HOST_RST reg_sdio_host_rst 7 1 read-write LCD_CAM_RST reg_lcd_cam_rst 8 1 read-write UART2_RST reg_uart2_rst 9 1 read-write TSENS_RST reg_tsens_rst 10 1 read-write BT_LPCK_DIV_INT clock config register 0x20 0x20 0x000000FF BT_LPCK_DIV_NUM reg_bt_lpck_div_num 0 12 read-write BT_LPCK_DIV_FRAC clock config register 0x24 0x20 0x02001001 BT_LPCK_DIV_B reg_bt_lpck_div_b 0 12 read-write BT_LPCK_DIV_A reg_bt_lpck_div_a 12 12 read-write LPCLK_SEL_RTC_SLOW reg_lpclk_sel_rtc_slow 24 1 read-write LPCLK_SEL_8M reg_lpclk_sel_8m 25 1 read-write LPCLK_SEL_XTAL reg_lpclk_sel_xtal 26 1 read-write LPCLK_SEL_XTAL32K reg_lpclk_sel_xtal32k 27 1 read-write LPCLK_RTC_EN reg_lpclk_rtc_en 28 1 read-write CPU_INTR_FROM_CPU_0 interrupt generate register 0x28 0x20 CPU_INTR_FROM_CPU_0 reg_cpu_intr_from_cpu_0 0 1 read-write CPU_INTR_FROM_CPU_1 interrupt generate register 0x2C 0x20 CPU_INTR_FROM_CPU_1 reg_cpu_intr_from_cpu_1 0 1 read-write CPU_INTR_FROM_CPU_2 interrupt generate register 0x30 0x20 CPU_INTR_FROM_CPU_2 reg_cpu_intr_from_cpu_2 0 1 read-write CPU_INTR_FROM_CPU_3 interrupt generate register 0x34 0x20 CPU_INTR_FROM_CPU_3 reg_cpu_intr_from_cpu_3 0 1 read-write RSA_PD_CTRL rsa memory power control register 0x38 0x20 0x00000001 RSA_MEM_PD reg_rsa_mem_pd 0 1 read-write RSA_MEM_FORCE_PU reg_rsa_mem_force_pu 1 1 read-write RSA_MEM_FORCE_PD reg_rsa_mem_force_pd 2 1 read-write EDMA_CTRL edma clcok and reset register 0x3C 0x20 0x00000001 EDMA_CLK_ON reg_edma_clk_on 0 1 read-write EDMA_RESET reg_edma_reset 1 1 read-write CACHE_CONTROL cache control register 0x40 0x20 0x00000005 ICACHE_CLK_ON reg_icache_clk_on 0 1 read-write ICACHE_RESET reg_icache_reset 1 1 read-write DCACHE_CLK_ON reg_dcache_clk_on 2 1 read-write DCACHE_RESET reg_dcache_reset 3 1 read-write EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG 0x44 0x20 ENABLE_SPI_MANUAL_ENCRYPT reg_enable_spi_manual_encrypt 0 1 read-write ENABLE_DOWNLOAD_DB_ENCRYPT reg_enable_download_db_encrypt 1 1 read-write ENABLE_DOWNLOAD_G0CB_DECRYPT reg_enable_download_g0cb_decrypt 2 1 read-write ENABLE_DOWNLOAD_MANUAL_ENCRYPT reg_enable_download_manual_encrypt 3 1 read-write RTC_FASTMEM_CONFIG fast memory config register 0x48 0x20 0x7FF00000 RTC_MEM_CRC_START reg_rtc_mem_crc_start 8 1 read-write RTC_MEM_CRC_ADDR reg_rtc_mem_crc_addr 9 11 read-write RTC_MEM_CRC_LEN reg_rtc_mem_crc_len 20 11 read-write RTC_MEM_CRC_FINISH reg_rtc_mem_crc_finish 31 1 read-only RTC_FASTMEM_CRC reserved 0x4C 0x20 RTC_MEM_CRC_RES reg_rtc_mem_crc_res 0 32 read-only REDUNDANT_ECO_CTRL eco register 0x50 0x20 REDUNDANT_ECO_DRIVE reg_redundant_eco_drive 0 1 read-write REDUNDANT_ECO_RESULT reg_redundant_eco_result 1 1 read-only CLOCK_GATE clock gating register 0x54 0x20 0x00000001 CLK_EN reg_clk_en 0 1 read-write SYSCLK_CONF system clock config register 0x58 0x20 0x00000001 PRE_DIV_CNT reg_pre_div_cnt 0 10 read-write SOC_CLK_SEL reg_soc_clk_sel 10 2 read-write CLK_XTAL_FREQ reg_clk_xtal_freq 12 7 read-only CLK_DIV_EN reg_clk_div_en 19 1 read-only MEM_PVT mem pvt register 0x5C 0x20 0x00000003 MEM_PATH_LEN reg_mem_path_len 0 4 read-write MEM_ERR_CNT_CLR reg_mem_err_cnt_clr 4 1 write-only MONITOR_EN reg_mem_pvt_monitor_en 5 1 read-write MEM_TIMING_ERR_CNT reg_mem_timing_err_cnt 6 16 read-only MEM_VT_SEL reg_mem_vt_sel 22 2 read-write COMB_PVT_LVT_CONF mem pvt register 0x60 0x20 0x00000003 COMB_PATH_LEN_LVT reg_comb_path_len_lvt 0 5 read-write COMB_ERR_CNT_CLR_LVT reg_comb_err_cnt_clr_lvt 5 1 write-only COMB_PVT_MONITOR_EN_LVT reg_comb_pvt_monitor_en_lvt 6 1 read-write COMB_PVT_NVT_CONF mem pvt register 0x64 0x20 0x00000003 COMB_PATH_LEN_NVT reg_comb_path_len_nvt 0 5 read-write COMB_ERR_CNT_CLR_NVT reg_comb_err_cnt_clr_nvt 5 1 write-only COMB_PVT_MONITOR_EN_NVT reg_comb_pvt_monitor_en_nvt 6 1 read-write COMB_PVT_HVT_CONF mem pvt register 0x68 0x20 0x00000003 COMB_PATH_LEN_HVT reg_comb_path_len_hvt 0 5 read-write COMB_ERR_CNT_CLR_HVT reg_comb_err_cnt_clr_hvt 5 1 write-only COMB_PVT_MONITOR_EN_HVT reg_comb_pvt_monitor_en_hvt 6 1 read-write COMB_PVT_ERR_LVT_SITE0 mem pvt register 0x6C 0x20 COMB_TIMING_ERR_CNT_LVT_SITE0 reg_comb_timing_err_cnt_lvt_site0 0 16 read-only COMB_PVT_ERR_NVT_SITE0 mem pvt register 0x70 0x20 COMB_TIMING_ERR_CNT_NVT_SITE0 reg_comb_timing_err_cnt_nvt_site0 0 16 read-only COMB_PVT_ERR_HVT_SITE0 mem pvt register 0x74 0x20 COMB_TIMING_ERR_CNT_HVT_SITE0 reg_comb_timing_err_cnt_hvt_site0 0 16 read-only COMB_PVT_ERR_LVT_SITE1 mem pvt register 0x78 0x20 COMB_TIMING_ERR_CNT_LVT_SITE1 reg_comb_timing_err_cnt_lvt_site1 0 16 read-only COMB_PVT_ERR_NVT_SITE1 mem pvt register 0x7C 0x20 COMB_TIMING_ERR_CNT_NVT_SITE1 reg_comb_timing_err_cnt_nvt_site1 0 16 read-only COMB_PVT_ERR_HVT_SITE1 mem pvt register 0x80 0x20 COMB_TIMING_ERR_CNT_HVT_SITE1 reg_comb_timing_err_cnt_hvt_site1 0 16 read-only COMB_PVT_ERR_LVT_SITE2 mem pvt register 0x84 0x20 COMB_TIMING_ERR_CNT_LVT_SITE2 reg_comb_timing_err_cnt_lvt_site2 0 16 read-only COMB_PVT_ERR_NVT_SITE2 mem pvt register 0x88 0x20 COMB_TIMING_ERR_CNT_NVT_SITE2 reg_comb_timing_err_cnt_nvt_site2 0 16 read-only COMB_PVT_ERR_HVT_SITE2 mem pvt register 0x8C 0x20 COMB_TIMING_ERR_CNT_HVT_SITE2 reg_comb_timing_err_cnt_hvt_site2 0 16 read-only COMB_PVT_ERR_LVT_SITE3 mem pvt register 0x90 0x20 COMB_TIMING_ERR_CNT_LVT_SITE3 reg_comb_timing_err_cnt_lvt_site3 0 16 read-only COMB_PVT_ERR_NVT_SITE3 mem pvt register 0x94 0x20 COMB_TIMING_ERR_CNT_NVT_SITE3 reg_comb_timing_err_cnt_nvt_site3 0 16 read-only COMB_PVT_ERR_HVT_SITE3 mem pvt register 0x98 0x20 COMB_TIMING_ERR_CNT_HVT_SITE3 reg_comb_timing_err_cnt_hvt_site3 0 16 read-only SYSTEM_REG_DATE Version register 0xFFC 0x20 0x02007150 SYSTEM_REG_DATE reg_system_reg_date 0 28 read-write SYSTIMER System Timer SYSTIMER 0x60023000 0x0 0x78 registers SYSTIMER_TARGET0 37 SYSTIMER_TARGET1 38 SYSTIMER_TARGET2 39 CONF SYSTIMER_CONF. 0x0 0x20 0x46000000 SYSTIMER_CLK_FO systimer clock force on 0 1 read-write TARGET2_WORK_EN target2 work enable 22 1 read-write TARGET1_WORK_EN target1 work enable 23 1 read-write TARGET0_WORK_EN target0 work enable 24 1 read-write TIMER_UNIT1_CORE1_STALL_EN If timer unit1 is stalled when core1 stalled 25 1 read-write TIMER_UNIT1_CORE0_STALL_EN If timer unit1 is stalled when core0 stalled 26 1 read-write TIMER_UNIT0_CORE1_STALL_EN If timer unit0 is stalled when core1 stalled 27 1 read-write TIMER_UNIT0_CORE0_STALL_EN If timer unit0 is stalled when core0 stalled 28 1 read-write TIMER_UNIT1_WORK_EN timer unit1 work enable 29 1 read-write TIMER_UNIT0_WORK_EN timer unit0 work enable 30 1 read-write CLK_EN register file clk gating 31 1 read-write UNIT0_OP SYSTIMER_UNIT0_OP. 0x4 0x20 TIMER_UNIT0_VALUE_VALID reg_timer_unit0_value_valid 29 1 read-only TIMER_UNIT0_UPDATE update timer_unit0 30 1 write-only UNIT1_OP SYSTIMER_UNIT1_OP. 0x8 0x20 TIMER_UNIT1_VALUE_VALID timer value is sync and valid 29 1 read-only TIMER_UNIT1_UPDATE update timer unit1 30 1 write-only UNIT0_LOAD_HI SYSTIMER_UNIT0_LOAD_HI. 0xC 0x20 TIMER_UNIT0_LOAD_HI timer unit0 load high 32 bit 0 20 read-write UNIT0_LOAD_LO SYSTIMER_UNIT0_LOAD_LO. 0x10 0x20 TIMER_UNIT0_LOAD_LO timer unit0 load low 32 bit 0 32 read-write UNIT1_LOAD_HI SYSTIMER_UNIT1_LOAD_HI. 0x14 0x20 TIMER_UNIT1_LOAD_HI timer unit1 load high 32 bit 0 20 read-write UNIT1_LOAD_LO SYSTIMER_UNIT1_LOAD_LO. 0x18 0x20 TIMER_UNIT1_LOAD_LO timer unit1 load low 32 bit 0 32 read-write TARGET0_HI SYSTIMER_TARGET0_HI. 0x1C 0x20 TIMER_TARGET0_HI timer taget0 high 32 bit 0 20 read-write TARGET0_LO SYSTIMER_TARGET0_LO. 0x20 0x20 TIMER_TARGET0_LO timer taget0 low 32 bit 0 32 read-write TARGET1_HI SYSTIMER_TARGET1_HI. 0x24 0x20 TIMER_TARGET1_HI timer taget1 high 32 bit 0 20 read-write TARGET1_LO SYSTIMER_TARGET1_LO. 0x28 0x20 TIMER_TARGET1_LO timer taget1 low 32 bit 0 32 read-write TARGET2_HI SYSTIMER_TARGET2_HI. 0x2C 0x20 TIMER_TARGET2_HI timer taget2 high 32 bit 0 20 read-write TARGET2_LO SYSTIMER_TARGET2_LO. 0x30 0x20 TIMER_TARGET2_LO timer taget2 low 32 bit 0 32 read-write TARGET0_CONF SYSTIMER_TARGET0_CONF. 0x34 0x20 TARGET0_PERIOD target0 period 0 26 read-write TARGET0_PERIOD_MODE Set target0 to period mode 30 1 read-write TARGET0_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET1_CONF SYSTIMER_TARGET1_CONF. 0x38 0x20 TARGET1_PERIOD target1 period 0 26 read-write TARGET1_PERIOD_MODE Set target1 to period mode 30 1 read-write TARGET1_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET2_CONF SYSTIMER_TARGET2_CONF. 0x3C 0x20 TARGET2_PERIOD target2 period 0 26 read-write TARGET2_PERIOD_MODE Set target2 to period mode 30 1 read-write TARGET2_TIMER_UNIT_SEL select which unit to compare 31 1 read-write UNIT0_VALUE_HI SYSTIMER_UNIT0_VALUE_HI. 0x40 0x20 TIMER_UNIT0_VALUE_HI timer read value high 32bit 0 20 read-only UNIT0_VALUE_LO SYSTIMER_UNIT0_VALUE_LO. 0x44 0x20 TIMER_UNIT0_VALUE_LO timer read value low 32bit 0 32 read-only UNIT1_VALUE_HI SYSTIMER_UNIT1_VALUE_HI. 0x48 0x20 TIMER_UNIT1_VALUE_HI timer read value high 32bit 0 20 read-only UNIT1_VALUE_LO SYSTIMER_UNIT1_VALUE_LO. 0x4C 0x20 TIMER_UNIT1_VALUE_LO timer read value low 32bit 0 32 read-only COMP0_LOAD SYSTIMER_COMP0_LOAD. 0x50 0x20 TIMER_COMP0_LOAD timer comp0 load value 0 1 write-only COMP1_LOAD SYSTIMER_COMP1_LOAD. 0x54 0x20 TIMER_COMP1_LOAD timer comp1 load value 0 1 write-only COMP2_LOAD SYSTIMER_COMP2_LOAD. 0x58 0x20 TIMER_COMP2_LOAD timer comp2 load value 0 1 write-only UNIT0_LOAD SYSTIMER_UNIT0_LOAD. 0x5C 0x20 TIMER_UNIT0_LOAD timer unit0 load value 0 1 write-only UNIT1_LOAD SYSTIMER_UNIT1_LOAD. 0x60 0x20 TIMER_UNIT1_LOAD timer unit1 load value 0 1 write-only INT_ENA SYSTIMER_INT_ENA. 0x64 0x20 TARGET0_INT_ENA interupt0 enable 0 1 read-write TARGET1_INT_ENA interupt1 enable 1 1 read-write TARGET2_INT_ENA interupt2 enable 2 1 read-write INT_RAW SYSTIMER_INT_RAW. 0x68 0x20 TARGET0_INT_RAW interupt0 raw 0 1 read-only TARGET1_INT_RAW interupt1 raw 1 1 read-only TARGET2_INT_RAW interupt2 raw 2 1 read-only INT_CLR SYSTIMER_INT_CLR. 0x6C 0x20 TARGET0_INT_CLR interupt0 clear 0 1 write-only TARGET1_INT_CLR interupt1 clear 1 1 write-only TARGET2_INT_CLR interupt2 clear 2 1 write-only INT_ST SYSTIMER_INT_ST. 0x70 0x20 TARGET0_INT_ST reg_target0_int_st 0 1 read-only TARGET1_INT_ST reg_target1_int_st 1 1 read-only TARGET2_INT_ST reg_target2_int_st 2 1 read-only DATE SYSTIMER_DATE. 0xFC 0x20 0x02006171 DATE reg_date 0 32 read-write TIMG0 Timer Group TIMG 0x6001F000 0x0 0x68 registers TG0_T0_LEVEL 32 TG0_WDT_LEVEL 33 T0CONFIG TIMG_T0CONFIG_REG. 0x0 0x20 0x60002000 USE_XTAL reg_t0_use_xtal. 9 1 read-write ALARM_EN reg_t0_alarm_en. 10 1 read-write DIVCNT_RST reg_t0_divcnt_rst. 12 1 write-only DIVIDER reg_t0_divider. 13 16 read-write AUTORELOAD reg_t0_autoreload. 29 1 read-write INCREASE reg_t0_increase. 30 1 read-write EN reg_t0_en. 31 1 read-write T0LO TIMG_T0LO_REG. 0x4 0x20 LO t0_lo 0 32 read-only T0HI TIMG_T0HI_REG. 0x8 0x20 HI t0_hi 0 22 read-only T0UPDATE TIMG_T0UPDATE_REG. 0xC 0x20 UPDATE t0_update 31 1 read-write T0ALARMLO TIMG_T0ALARMLO_REG. 0x10 0x20 ALARM_LO reg_t0_alarm_lo. 0 32 read-write T0ALARMHI TIMG_T0ALARMHI_REG. 0x14 0x20 ALARM_HI reg_t0_alarm_hi. 0 22 read-write T0LOADLO TIMG_T0LOADLO_REG. 0x18 0x20 LOAD_LO reg_t0_load_lo. 0 32 read-write T0LOADHI TIMG_T0LOADHI_REG. 0x1C 0x20 LOAD_HI reg_t0_load_hi. 0 22 read-write T0LOAD TIMG_T0LOAD_REG. 0x20 0x20 LOAD t0_load 0 32 write-only WDTCONFIG0 TIMG_WDTCONFIG0_REG. 0x48 0x20 0x0004C000 WDT_APPCPU_RESET_EN reg_wdt_appcpu_reset_en. 12 1 read-write WDT_PROCPU_RESET_EN reg_wdt_procpu_reset_en. 13 1 read-write WDT_FLASHBOOT_MOD_EN reg_wdt_flashboot_mod_en. 14 1 read-write WDT_SYS_RESET_LENGTH reg_wdt_sys_reset_length. 15 3 read-write WDT_CPU_RESET_LENGTH reg_wdt_cpu_reset_length. 18 3 read-write WDT_USE_XTAL reg_wdt_use_xtal. 21 1 read-write WDT_CONF_UPDATE_EN reg_wdt_conf_update_en. 22 1 write-only WDT_STG3 reg_wdt_stg3. 23 2 read-write WDT_STG2 reg_wdt_stg2. 25 2 read-write WDT_STG1 reg_wdt_stg1. 27 2 read-write WDT_STG0 reg_wdt_stg0. 29 2 read-write WDT_EN reg_wdt_en. 31 1 read-write WDTCONFIG1 TIMG_WDTCONFIG1_REG. 0x4C 0x20 0x00010000 WDT_DIVCNT_RST reg_wdt_divcnt_rst. 0 1 write-only WDT_CLK_PRESCALE reg_wdt_clk_prescale. 16 16 read-write WDTCONFIG2 TIMG_WDTCONFIG2_REG. 0x50 0x20 0x018CBA80 WDT_STG0_HOLD reg_wdt_stg0_hold. 0 32 read-write WDTCONFIG3 TIMG_WDTCONFIG3_REG. 0x54 0x20 0x07FFFFFF WDT_STG1_HOLD reg_wdt_stg1_hold. 0 32 read-write WDTCONFIG4 TIMG_WDTCONFIG4_REG. 0x58 0x20 0x000FFFFF WDT_STG2_HOLD reg_wdt_stg2_hold. 0 32 read-write WDTCONFIG5 TIMG_WDTCONFIG5_REG. 0x5C 0x20 0x000FFFFF WDT_STG3_HOLD reg_wdt_stg3_hold. 0 32 read-write WDTFEED TIMG_WDTFEED_REG. 0x60 0x20 WDT_FEED wdt_feed 0 32 write-only WDTWPROTECT TIMG_WDTWPROTECT_REG. 0x64 0x20 0x50D83AA1 WDT_WKEY reg_wdt_wkey. 0 32 read-write RTCCALICFG TIMG_RTCCALICFG_REG. 0x68 0x20 0x00013000 RTC_CALI_START_CYCLING reg_rtc_cali_start_cycling. 12 1 read-write RTC_CALI_CLK_SEL reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k 13 2 read-write RTC_CALI_RDY rtc_cali_rdy 15 1 read-only RTC_CALI_MAX reg_rtc_cali_max. 16 15 read-write RTC_CALI_START reg_rtc_cali_start. 31 1 read-write RTCCALICFG1 TIMG_RTCCALICFG1_REG. 0x6C 0x20 RTC_CALI_CYCLING_DATA_VLD rtc_cali_cycling_data_vld 0 1 read-only RTC_CALI_VALUE rtc_cali_value 7 25 read-only INT_ENA_TIMERS INT_ENA_TIMG_REG 0x70 0x20 T0_INT_ENA t0_int_ena 0 1 read-write WDT_INT_ENA wdt_int_ena 1 1 read-write INT_RAW_TIMERS INT_RAW_TIMG_REG 0x74 0x20 T0_INT_RAW t0_int_raw 0 1 read-only WDT_INT_RAW wdt_int_raw 1 1 read-only INT_ST_TIMERS INT_ST_TIMG_REG 0x78 0x20 T0_INT_ST t0_int_st 0 1 read-only WDT_INT_ST wdt_int_st 1 1 read-only INT_CLR_TIMERS INT_CLR_TIMG_REG 0x7C 0x20 T0_INT_CLR t0_int_clr 0 1 write-only WDT_INT_CLR wdt_int_clr 1 1 write-only RTCCALICFG2 TIMG_RTCCALICFG2_REG. 0x80 0x20 0xFFFFFF98 RTC_CALI_TIMEOUT timeoutindicator 0 1 read-only RTC_CALI_TIMEOUT_RST_CNT reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset 3 4 read-write RTC_CALI_TIMEOUT_THRES reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold 7 25 read-write NTIMG_DATE TIMG_NTIMG_DATE_REG. 0xF8 0x20 0x02006191 NTIMGS_DATE reg_ntimers_date. 0 28 read-write REGCLK TIMG_REGCLK_REG. 0xFC 0x20 0x60000000 WDT_CLK_IS_ACTIVE reg_wdt_clk_is_active. 29 1 read-write TIMER_CLK_IS_ACTIVE reg_timer_clk_is_active. 30 1 read-write CLK_EN reg_clk_en. 31 1 read-write TIMG1 Timer Group 0x60020000 TG1_T0_LEVEL 34 TG1_WDT_LEVEL 35 TWAI Two-Wire Automotive Interface TWAI 0x6002B000 0x0 0x6C registers TWAI 25 MODE Mode Register 0x0 0x20 0x00000001 RESET_MODE This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. 0 1 read-write LISTEN_ONLY_MODE 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. 1 1 read-write SELF_TEST_MODE 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. 2 1 read-write RX_FILTER_MODE This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. 3 1 read-write CMD Command Register 0x4 0x20 TX_REQ Set the bit to 1 to allow the driving nodes start transmission. 0 1 write-only ABORT_TX Set the bit to 1 to cancel a pending transmission request. 1 1 write-only RELEASE_BUF Set the bit to 1 to release the RX buffer. 2 1 write-only CLR_OVERRUN Set the bit to 1 to clear the data overrun status bit. 3 1 write-only SELF_RX_REQ Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. 4 1 write-only STATUS Status register 0x8 0x20 RX_BUF_ST 1: The data in the RX buffer is not empty, with at least one received data packet. 0 1 read-only OVERRUN_ST 1: The RX FIFO is full and data overrun has occurred. 1 1 read-only TX_BUF_ST 1: The TX buffer is empty, the CPU may write a message into it. 2 1 read-only TX_COMPLETE 1: The TWAI controller has successfully received a packet from the bus. 3 1 read-only RX_ST 1: The TWAI Controller is receiving a message from the bus. 4 1 read-only TX_ST 1: The TWAI Controller is transmitting a message to the bus. 5 1 read-only ERR_ST 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. 6 1 read-only BUS_OFF_ST 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. 7 1 read-only MISS_ST This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete 8 1 read-only INT_RAW Interrupt Register 0xC 0x20 RX_INT_ST Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. 0 1 read-only TX_INT_ST Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. 1 1 read-only ERR_WARN_INT_ST Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). 2 1 read-only OVERRUN_INT_ST Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. 3 1 read-only ERR_PASSIVE_INT_ST Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. 5 1 read-only ARB_LOST_INT_ST Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. 6 1 read-only BUS_ERR_INT_ST Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. 7 1 read-only INT_ENA Interrupt Enable Register 0x10 0x20 RX_INT_ENA Set this bit to 1 to enable receive interrupt. 0 1 read-write TX_INT_ENA Set this bit to 1 to enable transmit interrupt. 1 1 read-write ERR_WARN_INT_ENA Set this bit to 1 to enable error warning interrupt. 2 1 read-write OVERRUN_INT_ENA Set this bit to 1 to enable data overrun interrupt. 3 1 read-write ERR_PASSIVE_INT_ENA Set this bit to 1 to enable error passive interrupt. 5 1 read-write ARB_LOST_INT_ENA Set this bit to 1 to enable arbitration lost interrupt. 6 1 read-write BUS_ERR_INT_ENA Set this bit to 1 to enable error interrupt. 7 1 read-write BUS_TIMING_0 Bus Timing Register 0 0x18 0x20 BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 read-write BUS_TIMING_1 Bus Timing Register 1 0x1C 0x20 TIME_SEG1 The width of PBS1. 0 4 read-write TIME_SEG2 The width of PBS2. 4 3 read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 read-write ARB_LOST_CAP Arbitration Lost Capture Register 0x2C 0x20 ARB_LOST_CAP This register contains information about the bit position of lost arbitration. 0 5 read-only ERR_CODE_CAP Error Code Capture Register 0x30 0x20 ECC_SEGMENT This register contains information about the location of errors, see Table 181 for details. 0 5 read-only ECC_DIRECTION This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message 5 1 read-only ECC_TYPE This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error 6 2 read-only ERR_WARNING_LIMIT Error Warning Limit Register 0x34 0x20 0x00000060 ERR_WARNING_LIMIT Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 read-write RX_ERR_CNT Receive Error Counter Register 0x38 0x20 RX_ERR_CNT The RX error counter register, reflects value changes under reception status. 0 8 read-write TX_ERR_CNT Transmit Error Counter Register 0x3C 0x20 TX_ERR_CNT The TX error counter register, reflects value changes under transmission status. 0 8 read-write DATA_0 Data register 0 0x40 0x20 TX_BYTE_0 In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_1 Data register 1 0x44 0x20 TX_BYTE_1 In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_2 Data register 2 0x48 0x20 TX_BYTE_2 In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_3 Data register 3 0x4C 0x20 TX_BYTE_3 In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_4 Data register 4 0x50 0x20 TX_BYTE_4 In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_5 Data register 5 0x54 0x20 TX_BYTE_5 In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_6 Data register 6 0x58 0x20 TX_BYTE_6 In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_7 Data register 7 0x5C 0x20 TX_BYTE_7 In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_8 Data register 8 0x60 0x20 TX_BYTE_8 In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_9 Data register 9 0x64 0x20 TX_BYTE_9 In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_10 Data register 10 0x68 0x20 TX_BYTE_10 In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_11 Data register 11 0x6C 0x20 TX_BYTE_11 In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write DATA_12 Data register 12 0x70 0x20 TX_BYTE_12 In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 read-write RX_MESSAGE_CNT Receive Message Counter Register 0x74 0x20 RX_MESSAGE_COUNTER This register reflects the number of messages available within the RX FIFO. 0 7 read-only CLOCK_DIVIDER Clock Divider register 0x7C 0x20 CD These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. 0 8 read-write CLOCK_OFF This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 read-write UART0 UART (Universal Asynchronous Receiver-Transmitter) Controller UART 0x60000000 0x0 0x84 registers UART0 21 FIFO FIFO data register 0x0 0x20 RXFIFO_RD_BYTE UART 0 accesses FIFO via this register. 0 8 read-write INT_RAW Raw interrupt status 0x4 0x20 0x00000002 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 read-only TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 read-only PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 read-only FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 read-only RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 read-only DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 read-only CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 read-only BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 read-only RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 read-only SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 read-only SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 read-only GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 read-only TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. 12 1 read-only TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 read-only TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 read-only RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 read-only RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 read-only RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 read-only AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 read-only WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 read-only INT_ST Masked interrupt status 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 14 1 read-only RS485_PARITY_ERR_INT_ST This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. 15 1 read-only RS485_FRM_ERR_INT_ST This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. 16 1 read-only RS485_CLASH_INT_ST This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. 17 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. 18 1 read-only WAKEUP_INT_ST This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for rxfifo_full_int_st register. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for txfifo_empty_int_st register. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for parity_err_int_st register. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for frm_err_int_st register. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for dsr_chg_int_st register. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for cts_chg_int_st register. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for brk_det_int_st register. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write SW_XON_INT_ENA This is the enable bit for sw_xon_int_st register. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for sw_xoff_int_st register. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for glitch_det_int_st register. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for tx_brk_done_int_st register. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for tx_brk_idle_done_int_st register. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for tx_done_int_st register. 14 1 read-write RS485_PARITY_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 15 1 read-write RS485_FRM_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 16 1 read-write RS485_CLASH_INT_ENA This is the enable bit for rs485_clash_int_st register. 17 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for at_cmd_char_det_int_st register. 18 1 read-write WAKEUP_INT_ENA This is the enable bit for uart_wakeup_int_st register. 19 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear parity_err_int_raw interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear frm_err_int_raw interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear rxfifo_ovf_int_raw interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear the dsr_chg_int_raw interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear the cts_chg_int_raw interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear the brk_det_int_raw interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear the rxfifo_tout_int_raw interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear the sw_xoff_int_raw interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear the glitch_det_int_raw interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear the tx_done_int_raw interrupt. 14 1 write-only RS485_PARITY_ERR_INT_CLR Set this bit to clear the rs485_parity_err_int_raw interrupt. 15 1 write-only RS485_FRM_ERR_INT_CLR Set this bit to clear the rs485_frm_err_int_raw interrupt. 16 1 write-only RS485_CLASH_INT_CLR Set this bit to clear the rs485_clash_int_raw interrupt. 17 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the at_cmd_char_det_int_raw interrupt. 18 1 write-only WAKEUP_INT_CLR Set this bit to clear the uart_wakeup_int_raw interrupt. 19 1 write-only CLKDIV Clock divider configuration 0x14 0x20 0x000002B6 CLKDIV The integral part of the frequency divider factor. 0 12 read-write FRAG The decimal part of the frequency divider factor. 20 4 read-write RX_FILT Rx Filter configuration 0x18 0x20 0x00000008 GLITCH_FILT when input pulse width is lower than this value, the pulse is ignored. 0 8 read-write GLITCH_FILT_EN Set this bit to enable Rx signal filter. 8 1 read-write STATUS UART status register 0x1C 0x20 0xE000C000 RXFIFO_CNT Stores the byte number of valid data in Rx-FIFO. 0 10 read-only DSRN The register represent the level value of the internal uart dsr signal. 13 1 read-only CTSN This register represent the level value of the internal uart cts signal. 14 1 read-only RXD This register represent the level value of the internal uart rxd signal. 15 1 read-only TXFIFO_CNT Stores the byte number of data in Tx-FIFO. 16 10 read-only DTRN This bit represents the level of the internal uart dtr signal. 29 1 read-only RTSN This bit represents the level of the internal uart rts signal. 30 1 read-only TXD This bit represents the level of the internal uart txd signal. 31 1 read-only CONF0 a 0x20 0x20 0x1000001C PARITY This register is used to configure the parity check mode. 0 1 read-write PARITY_EN Set this bit to enable uart parity check. 1 1 read-write BIT_NUM This register is used to set the length of data. 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 4 2 read-write SW_RTS This register is used to configure the software rts signal which is used in software flow control. 6 1 read-write SW_DTR This register is used to configure the software dtr signal which is used in software flow control. 7 1 read-write TXD_BRK Set this bit to enbale transmitter to send NULL when the process of sending data is done. 8 1 read-write IRDA_DPLX Set this bit to enable IrDA loopback mode. 9 1 read-write IRDA_TX_EN This is the start enable bit for IrDA transmitter. 10 1 read-write IRDA_WCTL 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. 11 1 read-write IRDA_TX_INV Set this bit to invert the level of IrDA transmitter. 12 1 read-write IRDA_RX_INV Set this bit to invert the level of IrDA receiver. 13 1 read-write LOOPBACK Set this bit to enable uart loopback test mode. 14 1 read-write TX_FLOW_EN Set this bit to enable flow control function for transmitter. 15 1 read-write IRDA_EN Set this bit to enable IrDA protocol. 16 1 read-write RXFIFO_RST Set this bit to reset the uart receive-FIFO. 17 1 read-write TXFIFO_RST Set this bit to reset the uart transmit-FIFO. 18 1 read-write RXD_INV Set this bit to inverse the level value of uart rxd signal. 19 1 read-write CTS_INV Set this bit to inverse the level value of uart cts signal. 20 1 read-write DSR_INV Set this bit to inverse the level value of uart dsr signal. 21 1 read-write TXD_INV Set this bit to inverse the level value of uart txd signal. 22 1 read-write RTS_INV Set this bit to inverse the level value of uart rts signal. 23 1 read-write DTR_INV Set this bit to inverse the level value of uart dtr signal. 24 1 read-write CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 25 1 read-write ERR_WR_MASK 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. 26 1 read-write AUTOBAUD_EN This is the enable bit for detecting baudrate. 27 1 read-write MEM_CLK_EN UART memory clock gate enable signal. 28 1 read-write CONF1 Configuration register 1 0x24 0x20 0x0000C060 RXFIFO_FULL_THRHD It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. 0 9 read-write TXFIFO_EMPTY_THRHD It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. 9 9 read-write DIS_RX_DAT_OVF Disable UART Rx data overflow detect. 18 1 read-write RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control works. 19 1 read-write RX_FLOW_EN This is the flow enable bit for UART receiver. 20 1 read-write RX_TOUT_EN This is the enble bit for uart receiver's timeout function. 21 1 read-write LOWPULSE Autobaud minimum low pulse duration register 0x28 0x20 0x00000FFF MIN_CNT This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. 0 12 read-only HIGHPULSE Autobaud minimum high pulse duration register 0x2C 0x20 0x00000FFF MIN_CNT This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. 0 12 read-only RXD_CNT Autobaud edge change count register 0x30 0x20 RXD_EDGE_CNT This register stores the count of rxd edge change. It is used in baud rate-detect process. 0 10 read-only FLOW_CONF Software flow-control configuration 0x34 0x20 SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. 0 1 read-write XONOFF_DEL Set this bit to remove flow control char from the received data. 1 1 read-write FORCE_XON Set this bit to enable the transmitter to go on sending data. 2 1 read-write FORCE_XOFF Set this bit to stop the transmitter from sending data. 3 1 read-write SEND_XON Set this bit to send Xon char. It is cleared by hardware automatically. 4 1 read-write SEND_XOFF Set this bit to send Xoff char. It is cleared by hardware automatically. 5 1 read-write SLEEP_CONF Sleep-mode configuration 0x38 0x20 0x000000F0 ACTIVE_THRESHOLD The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. 0 10 read-write SWFC_CONF0 Software flow-control character configuration 0x3C 0x20 0x000026E0 XOFF_THRESHOLD When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. 0 9 read-write XOFF_CHAR This register stores the Xoff flow control char. 9 8 read-write SWFC_CONF1 Software flow-control character configuration 0x40 0x20 0x00002200 XON_THRESHOLD When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. 0 9 read-write XON_CHAR This register stores the Xon flow control char. 9 8 read-write TXBRK_CONF Tx Break character configuration 0x44 0x20 0x0000000A TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. 0 8 read-write IDLE_CONF Frame-end idle configuration 0x48 0x20 0x00040100 RX_IDLE_THRHD It will produce frame end signal when receiver takes more time to receive one byte data than this register value. 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers. 10 10 read-write RS485_CONF RS485 mode configuration 0x4C 0x20 RS485_EN Set this bit to choose the rs485 mode. 0 1 read-write DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write RS485TX_RX_EN Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. 3 1 read-write RS485RXBY_TX_EN 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. 4 1 read-write RS485_RX_DLY_NUM This register is used to delay the receiver's internal data signal. 5 1 read-write RS485_TX_DLY_NUM This register is used to delay the transmitter's internal data signal. 6 4 read-write AT_CMD_PRECNT Pre-sequence timing configuration 0x50 0x20 0x00000901 PRE_IDLE_NUM This register is used to configure the idle duration time before the first at_cmd is received by receiver. 0 16 read-write AT_CMD_POSTCNT Post-sequence timing configuration 0x54 0x20 0x00000901 POST_IDLE_NUM This register is used to configure the duration time between the last at_cmd and the next data. 0 16 read-write AT_CMD_GAPTOUT Timeout configuration 0x58 0x20 0x0000000B RX_GAP_TOUT This register is used to configure the duration time between the at_cmd chars. 0 16 read-write AT_CMD_CHAR AT escape sequence detection configuration 0x5C 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of at_cmd char. 0 8 read-write CHAR_NUM This register is used to configure the num of continuous at_cmd chars received by receiver. 8 8 read-write MEM_CONF UART threshold and allocation configuration 0x60 0x20 0x000A0012 RX_SIZE This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. 1 3 read-write TX_SIZE This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. 4 3 read-write RX_FLOW_THRHD This register is used to configure the maximum amount of data that can be received when hardware flow control works. 7 9 read-write RX_TOUT_THRHD This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. 16 10 read-write MEM_FORCE_PD Set this bit to force power down UART memory. 26 1 read-write MEM_FORCE_PU Set this bit to force power up UART memory. 27 1 read-write MEM_TX_STATUS Tx-FIFO write and read offset address. 0x64 0x20 APB_TX_WADDR This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. 0 10 read-only TX_RADDR This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. 11 10 read-only MEM_RX_STATUS Rx-FIFO write and read offset address. 0x68 0x20 0x00080100 APB_RX_RADDR This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180. 0 10 read-only RX_WADDR This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180. 11 10 read-only FSM_STATUS UART transmit and receive status. 0x6C 0x20 ST_URX_OUT This is the status register of receiver. 0 4 read-only ST_UTX_OUT This is the status register of transmitter. 4 4 read-only POSPULSE Autobaud high pulse register 0x70 0x20 0x00000FFF POSEDGE_MIN_CNT This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. 0 12 read-only NEGPULSE Autobaud low pulse register 0x74 0x20 0x00000FFF NEGEDGE_MIN_CNT This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. 0 12 read-only CLK_CONF UART core clock configuration 0x78 0x20 0x03701000 SCLK_DIV_B The denominator of the frequency divider factor. 0 6 read-write SCLK_DIV_A The numerator of the frequency divider factor. 6 6 read-write SCLK_DIV_NUM The integral part of the frequency divider factor. 12 8 read-write SCLK_SEL UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. 20 2 read-write SCLK_EN Set this bit to enable UART Tx/Rx clock. 22 1 read-write RST_CORE Write 1 then write 0 to this bit, reset UART Tx/Rx. 23 1 read-write TX_SCLK_EN Set this bit to enable UART Tx clock. 24 1 read-write RX_SCLK_EN Set this bit to enable UART Rx clock. 25 1 read-write TX_RST_CORE Write 1 then write 0 to this bit, reset UART Tx. 26 1 read-write RX_RST_CORE Write 1 then write 0 to this bit, reset UART Rx. 27 1 read-write DATE UART Version register 0x7C 0x20 0x02008270 DATE This is the version register. 0 32 read-write ID UART ID register 0x80 0x20 0x40000500 ID This register is used to configure the uart_id. 0 30 read-write HIGH_SPEED This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. 30 1 read-write REG_UPDATE Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. 31 1 read-write UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller 0x60010000 UART1 22 UHCI0 Universal Host Controller Interface UHCI 0x60014000 0x0 0x84 registers UHCI0 15 CONF0 a 0x0 0x20 0x000006E0 TX_RST Write 1, then write 0 to this bit to reset decode state machine. 0 1 read-write RX_RST Write 1, then write 0 to this bit to reset encode state machine. 1 1 read-write UART0_CE Set this bit to link up HCI and UART0. 2 1 read-write UART1_CE Set this bit to link up HCI and UART1. 3 1 read-write SEPER_EN Set this bit to separate the data frame using a special char. 5 1 read-write HEAD_EN Set this bit to encode the data packet with a formatting header. 6 1 read-write CRC_REC_EN Set this bit to enable UHCI to receive the 16 bit CRC. 7 1 read-write UART_IDLE_EOF_EN If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. 8 1 read-write LEN_EOF_EN If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. 9 1 read-write ENCODE_CRC_EN Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. 10 1 read-write CLK_EN 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. 11 1 read-write UART_RX_BRK_EOF_EN If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. 12 1 read-write INT_RAW a 0x4 0x20 RX_START_INT_RAW a 0 1 read-only TX_START_INT_RAW a 1 1 read-only RX_HUNG_INT_RAW a 2 1 read-only TX_HUNG_INT_RAW a 3 1 read-only SEND_S_REG_Q_INT_RAW a 4 1 read-only SEND_A_REG_Q_INT_RAW a 5 1 read-only OUT_EOF_INT_RAW This is the interrupt raw bit. Triggered when there are some errors in EOF in the 6 1 read-only APP_CTRL0_INT_RAW Soft control int raw bit. 7 1 read-write APP_CTRL1_INT_RAW Soft control int raw bit. 8 1 read-write INT_ST a 0x8 0x20 RX_START_INT_ST a 0 1 read-only TX_START_INT_ST a 1 1 read-only RX_HUNG_INT_ST a 2 1 read-only TX_HUNG_INT_ST a 3 1 read-only SEND_S_REG_Q_INT_ST a 4 1 read-only SEND_A_REG_Q_INT_ST a 5 1 read-only OUTLINK_EOF_ERR_INT_ST a 6 1 read-only APP_CTRL0_INT_ST a 7 1 read-only APP_CTRL1_INT_ST a 8 1 read-only INT_ENA a 0xC 0x20 RX_START_INT_ENA a 0 1 read-write TX_START_INT_ENA a 1 1 read-write RX_HUNG_INT_ENA a 2 1 read-write TX_HUNG_INT_ENA a 3 1 read-write SEND_S_REG_Q_INT_ENA a 4 1 read-write SEND_A_REG_Q_INT_ENA a 5 1 read-write OUTLINK_EOF_ERR_INT_ENA a 6 1 read-write APP_CTRL0_INT_ENA a 7 1 read-write APP_CTRL1_INT_ENA a 8 1 read-write INT_CLR a 0x10 0x20 RX_START_INT_CLR a 0 1 write-only TX_START_INT_CLR a 1 1 write-only RX_HUNG_INT_CLR a 2 1 write-only TX_HUNG_INT_CLR a 3 1 write-only SEND_S_REG_Q_INT_CLR a 4 1 write-only SEND_A_REG_Q_INT_CLR a 5 1 write-only OUTLINK_EOF_ERR_INT_CLR a 6 1 write-only APP_CTRL0_INT_CLR a 7 1 write-only APP_CTRL1_INT_CLR a 8 1 write-only CONF1 a 0x14 0x20 0x00000033 CHECK_SUM_EN a 0 1 read-write CHECK_SEQ_EN a 1 1 read-write CRC_DISABLE a 2 1 read-write SAVE_HEAD a 3 1 read-write TX_CHECK_SUM_RE a 4 1 read-write TX_ACK_NUM_RE a 5 1 read-write WAIT_SW_START a 7 1 read-write SW_START a 8 1 read-write STATE0 a 0x18 0x20 RX_ERR_CAUSE a 0 3 read-only DECODE_STATE a 3 3 read-only STATE1 a 0x1C 0x20 ENCODE_STATE a 0 3 read-only ESCAPE_CONF a 0x20 0x20 0x00000033 TX_C0_ESC_EN a 0 1 read-write TX_DB_ESC_EN a 1 1 read-write TX_11_ESC_EN a 2 1 read-write TX_13_ESC_EN a 3 1 read-write RX_C0_ESC_EN a 4 1 read-write RX_DB_ESC_EN a 5 1 read-write RX_11_ESC_EN a 6 1 read-write RX_13_ESC_EN a 7 1 read-write HUNG_CONF a 0x24 0x20 0x00810810 TXFIFO_TIMEOUT a 0 8 read-write TXFIFO_TIMEOUT_SHIFT a 8 3 read-write TXFIFO_TIMEOUT_ENA a 11 1 read-write RXFIFO_TIMEOUT a 12 8 read-write RXFIFO_TIMEOUT_SHIFT a 20 3 read-write RXFIFO_TIMEOUT_ENA a 23 1 read-write ACK_NUM a 0x28 0x20 0x00000008 ACK_NUM a 0 3 read-write LOAD a 3 1 write-only RX_HEAD a 0x2C 0x20 RX_HEAD a 0 32 read-only QUICK_SENT a 0x30 0x20 SINGLE_SEND_NUM a 0 3 read-write SINGLE_SEND_EN a 3 1 read-write ALWAYS_SEND_NUM a 4 3 read-write ALWAYS_SEND_EN a 7 1 read-write REG_Q0_WORD0 a 0x34 0x20 SEND_Q0_WORD0 a 0 32 read-write REG_Q0_WORD1 a 0x38 0x20 SEND_Q0_WORD1 a 0 32 read-write REG_Q1_WORD0 a 0x3C 0x20 SEND_Q1_WORD0 a 0 32 read-write REG_Q1_WORD1 a 0x40 0x20 SEND_Q1_WORD1 a 0 32 read-write REG_Q2_WORD0 a 0x44 0x20 SEND_Q2_WORD0 a 0 32 read-write REG_Q2_WORD1 a 0x48 0x20 SEND_Q2_WORD1 a 0 32 read-write REG_Q3_WORD0 a 0x4C 0x20 SEND_Q3_WORD0 a 0 32 read-write REG_Q3_WORD1 a 0x50 0x20 SEND_Q3_WORD1 a 0 32 read-write REG_Q4_WORD0 a 0x54 0x20 SEND_Q4_WORD0 a 0 32 read-write REG_Q4_WORD1 a 0x58 0x20 SEND_Q4_WORD1 a 0 32 read-write REG_Q5_WORD0 a 0x5C 0x20 SEND_Q5_WORD0 a 0 32 read-write REG_Q5_WORD1 a 0x60 0x20 SEND_Q5_WORD1 a 0 32 read-write REG_Q6_WORD0 a 0x64 0x20 SEND_Q6_WORD0 a 0 32 read-write REG_Q6_WORD1 a 0x68 0x20 SEND_Q6_WORD1 a 0 32 read-write ESC_CONF0 a 0x6C 0x20 0x00DCDBC0 SEPER_CHAR a 0 8 read-write SEPER_ESC_CHAR0 a 8 8 read-write SEPER_ESC_CHAR1 a 16 8 read-write ESC_CONF1 a 0x70 0x20 0x00DDDBDB ESC_SEQ0 a 0 8 read-write ESC_SEQ0_CHAR0 a 8 8 read-write ESC_SEQ0_CHAR1 a 16 8 read-write ESC_CONF2 a 0x74 0x20 0x00DEDB11 ESC_SEQ1 a 0 8 read-write ESC_SEQ1_CHAR0 a 8 8 read-write ESC_SEQ1_CHAR1 a 16 8 read-write ESC_CONF3 a 0x78 0x20 0x00DFDB13 ESC_SEQ2 a 0 8 read-write ESC_SEQ2_CHAR0 a 8 8 read-write ESC_SEQ2_CHAR1 a 16 8 read-write PKT_THRES a 0x7C 0x20 0x00000080 PKT_THRS a 0 13 read-write DATE a 0x80 0x20 0x02007170 DATE a 0 32 read-write UHCI1 Universal Host Controller Interface 0x6000C000 USB_DEVICE Full-speed USB Serial/JTAG Controller USB_DEVICE 0x60043000 0x0 0x50 registers USB_SERIAL_JTAG 26 EP1 USB_DEVICE_EP1_REG. 0x0 0x20 RDWR_BYTE Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. 0 8 read-write EP1_CONF USB_DEVICE_EP1_CONF_REG. 0x4 0x20 0x00000002 WR_DONE Set this bit to indicate writing byte data to UART Tx FIFO is done. 0 1 write-only SERIAL_IN_EP_DATA_FREE 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. 1 1 read-only SERIAL_OUT_EP_DATA_AVAIL 1'b1: Indicate there is data in UART Rx FIFO. 2 1 read-only INT_RAW USB_DEVICE_INT_RAW_REG. 0x8 0x20 0x00000008 JTAG_IN_FLUSH_INT_RAW The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 read-only SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 read-only SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 read-only SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 read-only PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 read-only CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 read-only CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 read-only STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 read-only IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 read-only USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 read-only OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 read-only OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 read-only INT_ST USB_DEVICE_INT_ST_REG. 0xC 0x20 JTAG_IN_FLUSH_INT_ST The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-only SOF_INT_ST The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-only SERIAL_OUT_RECV_PKT_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-only SERIAL_IN_EMPTY_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-only PID_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-only CRC5_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-only CRC16_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-only STUFF_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-only IN_TOKEN_REC_IN_EP1_INT_ST The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-only USB_BUS_RESET_INT_ST The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-only OUT_EP1_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-only OUT_EP2_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-only INT_ENA USB_DEVICE_INT_ENA_REG. 0x10 0x20 JTAG_IN_FLUSH_INT_ENA The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-write SOF_INT_ENA The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-write SERIAL_OUT_RECV_PKT_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-write SERIAL_IN_EMPTY_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-write PID_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-write CRC5_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-write CRC16_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-write STUFF_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-write IN_TOKEN_REC_IN_EP1_INT_ENA The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-write USB_BUS_RESET_INT_ENA The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-write OUT_EP1_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-write OUT_EP2_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-write INT_CLR USB_DEVICE_INT_CLR_REG. 0x14 0x20 JTAG_IN_FLUSH_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 write-only SOF_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. 1 1 write-only SERIAL_OUT_RECV_PKT_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 write-only SERIAL_IN_EMPTY_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 write-only PID_ERR_INT_CLR Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. 4 1 write-only CRC5_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 write-only CRC16_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 write-only STUFF_ERR_INT_CLR Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 write-only IN_TOKEN_REC_IN_EP1_INT_CLR Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. 8 1 write-only USB_BUS_RESET_INT_CLR Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 write-only OUT_EP1_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 write-only OUT_EP2_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 write-only CONF0 USB_DEVICE_CONF0_REG. 0x18 0x20 0x00004200 PHY_SEL Select internal/external PHY 0 1 read-write EXCHG_PINS_OVERRIDE Enable software control USB D+ D- exchange 1 1 read-write EXCHG_PINS USB D+ D- exchange 2 1 read-write VREFH Control single-end input high threshold,1.76V to 2V, step 80mV 3 2 read-write VREFL Control single-end input low threshold,0.8V to 1.04V, step 80mV 5 2 read-write VREF_OVERRIDE Enable software control input threshold 7 1 read-write PAD_PULL_OVERRIDE Enable software control USB D+ D- pullup pulldown 8 1 read-write DP_PULLUP Control USB D+ pull up. 9 1 read-write DP_PULLDOWN Control USB D+ pull down. 10 1 read-write DM_PULLUP Control USB D- pull up. 11 1 read-write DM_PULLDOWN Control USB D- pull down. 12 1 read-write PULLUP_VALUE Control pull up value. 13 1 read-write USB_PAD_ENABLE Enable USB pad function. 14 1 read-write TEST USB_DEVICE_TEST_REG. 0x1C 0x20 ENABLE Enable test of the USB pad 0 1 read-write USB_OE USB pad oen in test 1 1 read-write TX_DP USB D+ tx value in test 2 1 read-write TX_DM USB D- tx value in test 3 1 read-write JFIFO_ST USB_DEVICE_JFIFO_ST_REG. 0x20 0x20 0x00000044 IN_FIFO_CNT JTAT in fifo counter. 0 2 read-only IN_FIFO_EMPTY 1: JTAG in fifo is empty. 2 1 read-only IN_FIFO_FULL 1: JTAG in fifo is full. 3 1 read-only OUT_FIFO_CNT JTAT out fifo counter. 4 2 read-only OUT_FIFO_EMPTY 1: JTAG out fifo is empty. 6 1 read-only OUT_FIFO_FULL 1: JTAG out fifo is full. 7 1 read-only IN_FIFO_RESET Write 1 to reset JTAG in fifo. 8 1 read-write OUT_FIFO_RESET Write 1 to reset JTAG out fifo. 9 1 read-write FRAM_NUM USB_DEVICE_FRAM_NUM_REG. 0x24 0x20 SOF_FRAME_INDEX Frame index of received SOF frame. 0 11 read-only IN_EP0_ST USB_DEVICE_IN_EP0_ST_REG. 0x28 0x20 0x00000001 IN_EP0_STATE State of IN Endpoint 0. 0 2 read-only IN_EP0_WR_ADDR Write data address of IN endpoint 0. 2 7 read-only IN_EP0_RD_ADDR Read data address of IN endpoint 0. 9 7 read-only IN_EP1_ST USB_DEVICE_IN_EP1_ST_REG. 0x2C 0x20 0x00000001 IN_EP1_STATE State of IN Endpoint 1. 0 2 read-only IN_EP1_WR_ADDR Write data address of IN endpoint 1. 2 7 read-only IN_EP1_RD_ADDR Read data address of IN endpoint 1. 9 7 read-only IN_EP2_ST USB_DEVICE_IN_EP2_ST_REG. 0x30 0x20 0x00000001 IN_EP2_STATE State of IN Endpoint 2. 0 2 read-only IN_EP2_WR_ADDR Write data address of IN endpoint 2. 2 7 read-only IN_EP2_RD_ADDR Read data address of IN endpoint 2. 9 7 read-only IN_EP3_ST USB_DEVICE_IN_EP3_ST_REG. 0x34 0x20 0x00000001 IN_EP3_STATE State of IN Endpoint 3. 0 2 read-only IN_EP3_WR_ADDR Write data address of IN endpoint 3. 2 7 read-only IN_EP3_RD_ADDR Read data address of IN endpoint 3. 9 7 read-only OUT_EP0_ST USB_DEVICE_OUT_EP0_ST_REG. 0x38 0x20 OUT_EP0_STATE State of OUT Endpoint 0. 0 2 read-only OUT_EP0_WR_ADDR Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. 2 7 read-only OUT_EP0_RD_ADDR Read data address of OUT endpoint 0. 9 7 read-only OUT_EP1_ST USB_DEVICE_OUT_EP1_ST_REG. 0x3C 0x20 OUT_EP1_STATE State of OUT Endpoint 1. 0 2 read-only OUT_EP1_WR_ADDR Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. 2 7 read-only OUT_EP1_RD_ADDR Read data address of OUT endpoint 1. 9 7 read-only OUT_EP1_REC_DATA_CNT Data count in OUT endpoint 1 when one packet is received. 16 7 read-only OUT_EP2_ST USB_DEVICE_OUT_EP2_ST_REG. 0x40 0x20 OUT_EP2_STATE State of OUT Endpoint 2. 0 2 read-only OUT_EP2_WR_ADDR Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. 2 7 read-only OUT_EP2_RD_ADDR Read data address of OUT endpoint 2. 9 7 read-only MISC_CONF USB_DEVICE_MISC_CONF_REG. 0x44 0x20 CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 0 1 read-write MEM_CONF USB_DEVICE_MEM_CONF_REG. 0x48 0x20 0x00000002 USB_MEM_PD 1: power down usb memory. 0 1 read-write USB_MEM_CLK_EN 1: Force clock on for usb memory. 1 1 read-write DATE USB_DEVICE_DATE_REG. 0x80 0x20 0x02007300 DATE register version. 0 32 read-write XTS_AES XTS-AES-128 Flash Encryption XTS_AES 0x600CC000 0x0 0x30 registers 16 0x1 PLAIN_MEM[%s] The memory that stores plaintext 0x0 0x8 LINESIZE XTS-AES line-size register 0x40 0x20 LINESIZE This bit stores the line size parameter. 0: 16Byte, 1: 32Byte. 0 1 read-write DESTINATION XTS-AES destination register 0x44 0x20 DESTINATION This bit stores the destination. 0: flash(default). 1: reserved. 0 1 read-write PHYSICAL_ADDRESS XTS-AES physical address register 0x48 0x20 PHYSICAL_ADDRESS Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. 0 30 read-write TRIGGER XTS-AES trigger register 0x4C 0x20 TRIGGER Set this bit to start manual encryption calculation 0 1 write-only RELEASE XTS-AES release register 0x50 0x20 RELEASE Set this bit to release the manual encrypted result, after that the result will be visible to spi 0 1 write-only DESTROY XTS-AES destroy register 0x54 0x20 DESTROY Set this bit to destroy XTS-AES result. 0 1 write-only STATE XTS-AES status register 0x58 0x20 STATE Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi. 0 2 read-only DATE XTS-AES version control register 0x5C 0x20 0x20200623 DATE Those bits stores the version information of XTS-AES. 0 30 read-write